drm/i915/psr/cnl: Enable Y-coordinate support in source
authorJosé Roberto de Souza <jose.souza@intel.com>
Wed, 28 Mar 2018 22:30:41 +0000 (15:30 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Fri, 30 Mar 2018 17:17:57 +0000 (10:17 -0700)
For Geminilake and Cannonlake+ the Y-coordinate support must be
enabled in PSR2_CTL too.

Spec: 7713 and 7720

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-5-jose.souza@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_psr.c

index b926520803b6006bc536eecaef99579aea46af62..6566f6bc54171c9871500d632672d00b0d6a79fd 100644 (file)
@@ -4058,6 +4058,8 @@ enum {
 #define EDP_PSR2_CTL                   _MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE              (1<<31)
 #define   EDP_SU_TRACK_ENABLE          (1<<30)
+#define   EDP_Y_COORDINATE_VALID       (1<<26) /* GLK and CNL+ */
+#define   EDP_Y_COORDINATE_ENABLE      (1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)   ((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
 #define   EDP_PSR2_TP2_TIME_500                (0<<8)
@@ -7042,6 +7044,7 @@ enum {
 #define CHICKEN_TRANS_A         0x420c0
 #define CHICKEN_TRANS_B         0x420c4
 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
 #define  DDI_TRAINING_OVERRIDE_ENABLE  (1<<19)
 #define  DDI_TRAINING_OVERRIDE_VALUE   (1<<18)
 #define  DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
index fb2d0fe7106b5aa0aba4161df2464ca223939a4b..84e1f8be5c488e254fc2fcb8fffcad8b483a3692 100644 (file)
@@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        /* FIXME: selective update is probably totally broken because it doesn't
         * mesh at all with our frontbuffer tracking. And the hw alone isn't
         * good enough. */
-       val |= EDP_PSR2_ENABLE |
-               EDP_SU_TRACK_ENABLE;
+       val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+       if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+               val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
+       }
 
        if (drm_dp_dpcd_readb(&intel_dp->aux,
                                DP_SYNCHRONIZATION_LATENCY_IN_SINK,
@@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
                hsw_psr_setup_aux(intel_dp);
 
        if (dev_priv->psr.psr2_support) {
-               u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
-                             | PSR2_ADD_VERTICAL_LINE_COUNT;
+               u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
+
+               if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+                       chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
+                                  | PSR2_ADD_VERTICAL_LINE_COUNT);
+
+               else
+                       chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
                I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
 
                I915_WRITE(EDP_PSR_DEBUG,