--- /dev/null
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+@@ -320,10 +320,6 @@
+ #define IS_SIM(chippkg) \
+ ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
+
+-#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
+-
+-#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
+-
+ #ifdef DEBUG
+ #define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
+ #else
+@@ -475,9 +471,6 @@ ai_buscore_setup(struct si_info *sii, st
+ sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
+ }
+
+- /* figure out buscore */
+- sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
+-
+ return true;
+ }
+
+@@ -485,11 +478,7 @@ static struct si_info *ai_doattach(struc
+ struct bcma_bus *pbus)
+ {
+ struct si_pub *sih = &sii->pub;
+- u32 w, savewin;
+ struct bcma_device *cc;
+- struct ssb_sprom *sprom = &pbus->sprom;
+-
+- savewin = 0;
+
+ sii->icbus = pbus;
+ sii->pcibus = pbus->host_pci;
+@@ -512,47 +501,7 @@ static struct si_info *ai_doattach(struc
+
+ /* PMU specific initializations */
+ if (ai_get_cccaps(sih) & CC_CAP_PMU) {
+- si_pmu_init(sih);
+ (void)si_pmu_measure_alpclk(sih);
+- si_pmu_res_init(sih);
+- }
+-
+- /* setup the GPIO based LED powersave register */
+- w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
+- (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
+- if (w == 0)
+- w = DEFAULT_GPIOTIMERVAL;
+- ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
+- ~0, w);
+-
+- if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
+- /*
+- * enable 12 mA drive strenth for 43224 and
+- * set chipControl register bit 15
+- */
+- if (ai_get_chiprev(sih) == 0) {
+- SI_MSG("Applying 43224A0 WARs\n");
+- ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
+- CCTRL43224_GPIO_TOGGLE,
+- CCTRL43224_GPIO_TOGGLE);
+- si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
+- CCTRL_43224A0_12MA_LED_DRIVE);
+- }
+- if (ai_get_chiprev(sih) >= 1) {
+- SI_MSG("Applying 43224B0+ WARs\n");
+- si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
+- CCTRL_43224B0_12MA_LED_DRIVE);
+- }
+- }
+-
+- if (ai_get_chip_id(sih) == BCM4313_CHIP_ID) {
+- /*
+- * enable 12 mA drive strenth for 4313 and
+- * set chipControl register bit 1
+- */
+- SI_MSG("Applying 4313 WARs\n");
+- si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
+- CCTRL_4313_12MA_LED_DRIVE);
+ }
+
+ return sii;
+@@ -591,7 +540,7 @@ void ai_detach(struct si_pub *sih)
+ struct si_pub *si_local = NULL;
+ memcpy(&si_local, &sih, sizeof(struct si_pub **));
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+
+ if (sii == NULL)
+ return;
+@@ -599,27 +548,6 @@ void ai_detach(struct si_pub *sih)
+ kfree(sii);
+ }
+
+-/* return index of coreid or BADIDX if not found */
+-struct bcma_device *ai_findcore(struct si_pub *sih, u16 coreid, u16 coreunit)
+-{
+- struct bcma_device *core;
+- struct si_info *sii;
+- uint found;
+-
+- sii = (struct si_info *)sih;
+-
+- found = 0;
+-
+- list_for_each_entry(core, &sii->icbus->cores, list)
+- if (core->id.id == coreid) {
+- if (found == coreunit)
+- return core;
+- found++;
+- }
+-
+- return NULL;
+-}
+-
+ /*
+ * read/modify chipcommon core register.
+ */
+@@ -629,7 +557,7 @@ uint ai_cc_reg(struct si_pub *sih, uint
+ u32 w;
+ struct si_info *sii;
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+ cc = sii->icbus->drv_cc.core;
+
+ /* mask and set */
+@@ -695,12 +623,13 @@ ai_clkctl_setdelay(struct si_pub *sih, s
+ /* initialize power control delay registers */
+ void ai_clkctl_init(struct si_pub *sih)
+ {
++ struct si_info *sii = container_of(sih, struct si_info, pub);
+ struct bcma_device *cc;
+
+ if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
+ return;
+
+- cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
++ cc = sii->icbus->drv_cc.core;
+ if (cc == NULL)
+ return;
+
+@@ -722,7 +651,7 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
+ uint slowminfreq;
+ u16 fpdelay;
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+ if (ai_get_cccaps(sih) & CC_CAP_PMU) {
+ fpdelay = si_pmu_fast_pwrup_delay(sih);
+ return fpdelay;
+@@ -732,7 +661,7 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
+ return 0;
+
+ fpdelay = 0;
+- cc = ai_findcore(sih, CC_CORE_ID, 0);
++ cc = sii->icbus->drv_cc.core;
+ if (cc) {
+ slowminfreq = ai_slowclk_freq(sih, false, cc);
+ fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2)
+@@ -754,12 +683,9 @@ bool ai_clkctl_cc(struct si_pub *sih, en
+ struct si_info *sii;
+ struct bcma_device *cc;
+
+- sii = (struct si_info *)sih;
+-
+- if (PCI_FORCEHT(sih))
+- return mode == BCMA_CLKMODE_FAST;
++ sii = container_of(sih, struct si_info, pub);
+
+- cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
++ cc = sii->icbus->drv_cc.core;
+ bcma_core_set_clockmode(cc, mode);
+ return mode == BCMA_CLKMODE_FAST;
+ }
+@@ -767,16 +693,10 @@ bool ai_clkctl_cc(struct si_pub *sih, en
+ void ai_pci_up(struct si_pub *sih)
+ {
+ struct si_info *sii;
+- struct bcma_device *cc;
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+
+- if (PCI_FORCEHT(sih)) {
+- cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
+- bcma_core_set_clockmode(cc, BCMA_CLKMODE_FAST);
+- }
+-
+- if (PCIE(sih))
++ if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
+ }
+
+@@ -784,26 +704,20 @@ void ai_pci_up(struct si_pub *sih)
+ void ai_pci_down(struct si_pub *sih)
+ {
+ struct si_info *sii;
+- struct bcma_device *cc;
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+
+- /* release FORCEHT since chip is going to "down" state */
+- if (PCI_FORCEHT(sih)) {
+- cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
+- bcma_core_set_clockmode(cc, BCMA_CLKMODE_DYNAMIC);
+- }
+-
+- if (PCIE(sih))
++ if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
+ }
+
+ /* Enable BT-COEX & Ex-PA for 4313 */
+ void ai_epa_4313war(struct si_pub *sih)
+ {
++ struct si_info *sii = container_of(sih, struct si_info, pub);
+ struct bcma_device *cc;
+
+- cc = ai_findcore(sih, CC_CORE_ID, 0);
++ cc = sii->icbus->drv_cc.core;
+
+ /* EPA Fix */
+ bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK);
+@@ -815,7 +729,7 @@ bool ai_deviceremoved(struct si_pub *sih
+ u32 w;
+ struct si_info *sii;
+
+- sii = (struct si_info *)sih;
++ sii = container_of(sih, struct si_info, pub);
+
+ if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
+ return false;
+@@ -826,15 +740,3 @@ bool ai_deviceremoved(struct si_pub *sih
+
+ return false;
+ }
+-
+-uint ai_get_buscoretype(struct si_pub *sih)
+-{
+- struct si_info *sii = (struct si_info *)sih;
+- return sii->buscore->id.id;
+-}
+-
+-uint ai_get_buscorerev(struct si_pub *sih)
+-{
+- struct si_info *sii = (struct si_info *)sih;
+- return sii->buscore->id.rev;
+-}
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+@@ -88,16 +88,6 @@
+ #define CLKD_OTP 0x000f0000
+ #define CLKD_OTP_SHIFT 16
+
+-/* Package IDs */
+-#define BCM4717_PKG_ID 9 /* 4717 package id */
+-#define BCM4718_PKG_ID 10 /* 4718 package id */
+-#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
+-
+-/* these are router chips */
+-#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
+-#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
+-#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
+-
+ /* dynamic clock control defines */
+ #define LPOMINFREQ 25000 /* low power oscillator min */
+ #define LPOMAXFREQ 43000 /* low power oscillator max */
+@@ -168,7 +158,6 @@ struct si_info {
+ struct si_pub pub; /* back plane public state (must be first) */
+ struct bcma_bus *icbus; /* handle to soc interconnect bus */
+ struct pci_dev *pcibus; /* handle to pci bus */
+- struct bcma_device *buscore;
+
+ u32 chipst; /* chip status */
+ };
+@@ -183,8 +172,6 @@ struct si_info {
+
+
+ /* AMBA Interconnect exported externs */
+-extern struct bcma_device *ai_findcore(struct si_pub *sih,
+- u16 coreid, u16 coreunit);
+ extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
+
+ /* === exported functions === */
+@@ -202,9 +189,6 @@ extern void ai_pci_up(struct si_pub *sih
+ /* Enable Ex-PA for 4313 */
+ extern void ai_epa_4313war(struct si_pub *sih);
+
+-extern uint ai_get_buscoretype(struct si_pub *sih);
+-extern uint ai_get_buscorerev(struct si_pub *sih);
+-
+ static inline u32 ai_get_cccaps(struct si_pub *sih)
+ {
+ return sih->cccaps;
+--- a/drivers/net/wireless/brcm80211/brcmsmac/dma.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
+@@ -574,6 +574,7 @@ struct dma_pub *dma_attach(char *name, s
+ struct dma_info *di;
+ u8 rev = core->id.rev;
+ uint size;
++ struct si_info *sii = container_of(sih, struct si_info, pub);
+
+ /* allocate private info structure */
+ di = kzalloc(sizeof(struct dma_info), GFP_ATOMIC);
+@@ -634,16 +635,20 @@ struct dma_pub *dma_attach(char *name, s
+ */
+ di->ddoffsetlow = 0;
+ di->dataoffsetlow = 0;
+- /* add offset for pcie with DMA64 bus */
+- di->ddoffsetlow = 0;
+- di->ddoffsethigh = SI_PCIE_DMA_H32;
++ /* for pci bus, add offset */
++ if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) {
++ /* add offset for pcie with DMA64 bus */
++ di->ddoffsetlow = 0;
++ di->ddoffsethigh = SI_PCIE_DMA_H32;
++ }
+ di->dataoffsetlow = di->ddoffsetlow;
+ di->dataoffsethigh = di->ddoffsethigh;
++
+ /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
+- if ((core->id.id == SDIOD_CORE_ID)
++ if ((core->id.id == BCMA_CORE_SDIO_DEV)
+ && ((rev > 0) && (rev <= 2)))
+ di->addrext = false;
+- else if ((core->id.id == I2S_CORE_ID) &&
++ else if ((core->id.id == BCMA_CORE_I2S) &&
+ ((rev == 0) || (rev == 1)))
+ di->addrext = false;
+ else
+--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+@@ -321,8 +321,7 @@ static void brcms_ops_stop(struct ieee80
+ return;
+
+ spin_lock_bh(&wl->lock);
+- status = brcms_c_chipmatch(wl->wlc->hw->vendorid,
+- wl->wlc->hw->deviceid);
++ status = brcms_c_chipmatch(wl->wlc->hw->d11core);
+ spin_unlock_bh(&wl->lock);
+ if (!status) {
+ wiphy_err(wl->wiphy,
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -271,7 +271,7 @@ struct brcms_c_bit_desc {
+ */
+
+ /* Starting corerev for the fifo size table */
+-#define XMTFIFOTBL_STARTREV 20
++#define XMTFIFOTBL_STARTREV 17
+
+ struct d11init {
+ __le16 addr;
+@@ -335,6 +335,12 @@ const u8 wlc_prio2prec_map[] = {
+ };
+
+ static const u16 xmtfifo_sz[][NFIFO] = {
++ /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
++ {20, 192, 192, 21, 17, 5},
++ /* corerev 18: */
++ {0, 0, 0, 0, 0, 0},
++ /* corerev 19: */
++ {0, 0, 0, 0, 0, 0},
+ /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
+ {20, 192, 192, 21, 17, 5},
+ /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
+@@ -345,6 +351,14 @@ static const u16 xmtfifo_sz[][NFIFO] = {
+ {20, 192, 192, 21, 17, 5},
+ /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
+ {9, 58, 22, 14, 14, 5},
++ /* corerev 25: */
++ {0, 0, 0, 0, 0, 0},
++ /* corerev 26: */
++ {0, 0, 0, 0, 0, 0},
++ /* corerev 27: */
++ {0, 0, 0, 0, 0, 0},
++ /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
++ {9, 58, 22, 14, 14, 5},
+ };
+
+ #ifdef DEBUG
+@@ -1944,7 +1958,8 @@ static bool brcms_b_radio_read_hwdisable
+ * accesses phyreg throughput mac. This can be skipped since
+ * only mac reg is accessed below
+ */
+- flags |= SICF_PCLKE;
++ if (D11REV_GE(wlc_hw->corerev, 18))
++ flags |= SICF_PCLKE;
+
+ /*
+ * TODO: test suspend/resume
+@@ -2025,7 +2040,8 @@ void brcms_b_corereset(struct brcms_hard
+ * phyreg throughput mac, AND phy_reset is skipped at early stage when
+ * band->pi is invalid. need to enable PHY CLK
+ */
+- flags |= SICF_PCLKE;
++ if (D11REV_GE(wlc_hw->corerev, 18))
++ flags |= SICF_PCLKE;
+
+ /*
+ * reset the core
+@@ -2128,8 +2144,8 @@ void brcms_b_switch_macfreq(struct brcms
+ {
+ struct bcma_device *core = wlc_hw->d11core;
+
+- if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
+- (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
++ if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
++ (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
+ if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
+ bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
+ bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
+@@ -2793,7 +2809,7 @@ void brcms_b_core_phypll_ctl(struct brcm
+ tmp = 0;
+
+ if (on) {
+- if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
++ if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
+ bcma_set32(core, D11REGOFFS(clk_ctl_st),
+ CCS_ERSRC_REQ_HT |
+ CCS_ERSRC_REQ_D11PLL |
+@@ -4220,9 +4236,8 @@ static void brcms_c_radio_timer(void *ar
+ }
+
+ /* common low-level watchdog code */
+-static void brcms_b_watchdog(void *arg)
++static void brcms_b_watchdog(struct brcms_c_info *wlc)
+ {
+- struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
+ struct brcms_hardware *wlc_hw = wlc->hw;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
+@@ -4243,10 +4258,8 @@ static void brcms_b_watchdog(void *arg)
+ }
+
+ /* common watchdog code */
+-static void brcms_c_watchdog(void *arg)
++static void brcms_c_watchdog(struct brcms_c_info *wlc)
+ {
+- struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
+-
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ if (!wlc->pub->up)
+@@ -4286,7 +4299,9 @@ static void brcms_c_watchdog(void *arg)
+
+ static void brcms_c_watchdog_by_timer(void *arg)
+ {
+- brcms_c_watchdog(arg);
++ struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
++
++ brcms_c_watchdog(wlc);
+ }
+
+ static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
+@@ -4456,11 +4471,9 @@ static int brcms_b_attach(struct brcms_c
+ }
+
+ /* verify again the device is supported */
+- if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
+- !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
+- wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
+- "vendor/device (0x%x/0x%x)\n",
+- unit, pcidev->vendor, pcidev->device);
++ if (!brcms_c_chipmatch(core)) {
++ wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
++ unit);
+ err = 12;
+ goto fail;
+ }
+@@ -4530,7 +4543,7 @@ static int brcms_b_attach(struct brcms_c
+ else
+ wlc_hw->_nbands = 1;
+
+- if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
++ if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
+ wlc_hw->_nbands = 1;
+
+ /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
+@@ -4597,8 +4610,12 @@ static int brcms_b_attach(struct brcms_c
+ wlc_hw->machwcap_backup = wlc_hw->machwcap;
+
+ /* init tx fifo size */
++ WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
++ (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
++ ARRAY_SIZE(xmtfifo_sz));
+ wlc_hw->xmtfifo_sz =
+ xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
++ WARN_ON(!wlc_hw->xmtfifo_sz[0]);
+
+ /* Get a phy for this band */
+ wlc_hw->band->pi =
+@@ -5038,7 +5055,7 @@ static void brcms_b_hw_up(struct brcms_h
+ wlc_hw->wlc->pub->hw_up = true;
+
+ if ((wlc_hw->boardflags & BFL_FEM)
+- && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
++ && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
+ if (!
+ (wlc_hw->boardrev >= 0x1250
+ && (wlc_hw->boardflags & BFL_FEM_BT)))
+@@ -5132,7 +5149,7 @@ int brcms_c_up(struct brcms_c_info *wlc)
+ }
+
+ if ((wlc->pub->boardflags & BFL_FEM)
+- && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
++ && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
+ if (wlc->pub->boardrev >= 0x1250
+ && (wlc->pub->boardflags & BFL_FEM_BT))
+ brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
+@@ -5769,8 +5786,12 @@ void brcms_c_print_txstatus(struct tx_st
+ (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
+ }
+
+-bool brcms_c_chipmatch(u16 vendor, u16 device)
++static bool brcms_c_chipmatch_pci(struct bcma_device *core)
+ {
++ struct pci_dev *pcidev = core->bus->host_pci;
++ u16 vendor = pcidev->vendor;
++ u16 device = pcidev->device;
++
+ if (vendor != PCI_VENDOR_ID_BROADCOM) {
+ pr_err("unknown vendor id %04x\n", vendor);
+ return false;
+@@ -5789,6 +5810,30 @@ bool brcms_c_chipmatch(u16 vendor, u16 d
+ return false;
+ }
+
++static bool brcms_c_chipmatch_soc(struct bcma_device *core)
++{
++ struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
++
++ if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
++ return true;
++
++ pr_err("unknown chip id %04x\n", chipinfo->id);
++ return false;
++}
++
++bool brcms_c_chipmatch(struct bcma_device *core)
++{
++ switch (core->bus->hosttype) {
++ case BCMA_HOSTTYPE_PCI:
++ return brcms_c_chipmatch_pci(core);
++ case BCMA_HOSTTYPE_SOC:
++ return brcms_c_chipmatch_soc(core);
++ default:
++ pr_err("unknown host type: %i\n", core->bus->hosttype);
++ return false;
++ }
++}
++
+ #if defined(DEBUG)
+ void brcms_c_print_txdesc(struct d11txh *txh)
+ {
+--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
+@@ -198,6 +198,8 @@ u16 read_radio_reg(struct brcms_phy *pi,
+
+ void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
+ {
++ struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
++
+ if ((D11REV_GE(pi->sh->corerev, 24)) ||
+ (D11REV_IS(pi->sh->corerev, 22)
+ && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
+@@ -209,7 +211,8 @@ void write_radio_reg(struct brcms_phy *p
+ bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
+ }
+
+- if (++pi->phy_wreg >= pi->phy_wreg_limit) {
++ if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
++ (++pi->phy_wreg >= pi->phy_wreg_limit)) {
+ (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
+ pi->phy_wreg = 0;
+ }
+@@ -292,10 +295,13 @@ void write_phy_reg(struct brcms_phy *pi,
+ bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
+ bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val);
+ if (addr == 0x72)
+- (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
++ (void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
+ #else
++ struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
++
+ bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
+- if (++pi->phy_wreg >= pi->phy_wreg_limit) {
++ if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
++ (++pi->phy_wreg >= pi->phy_wreg_limit)) {
+ pi->phy_wreg = 0;
+ (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
+ }
+@@ -837,7 +843,7 @@ wlc_phy_table_addr(struct brcms_phy *pi,
+ pi->tbl_data_hi = tblDataHi;
+ pi->tbl_data_lo = tblDataLo;
+
+- if (pi->sh->chip == BCM43224_CHIP_ID &&
++ if (pi->sh->chip == BCMA_CHIP_ID_BCM43224 &&
+ pi->sh->chiprev == 1) {
+ pi->tbl_addr = tblAddr;
+ pi->tbl_save_id = tbl_id;
+@@ -847,7 +853,7 @@ wlc_phy_table_addr(struct brcms_phy *pi,
+
+ void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
+ {
+- if ((pi->sh->chip == BCM43224_CHIP_ID) &&
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
+ (pi->sh->chiprev == 1) &&
+ (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
+ read_phy_reg(pi, pi->tbl_data_lo);
+@@ -881,7 +887,7 @@ wlc_phy_write_table(struct brcms_phy *pi
+
+ for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
+
+- if ((pi->sh->chip == BCM43224_CHIP_ID) &&
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
+ (pi->sh->chiprev == 1) &&
+ (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
+ read_phy_reg(pi, tblDataLo);
+@@ -918,7 +924,7 @@ wlc_phy_read_table(struct brcms_phy *pi,
+
+ for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
+
+- if ((pi->sh->chip == BCM43224_CHIP_ID) &&
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
+ (pi->sh->chiprev == 1)) {
+ (void)read_phy_reg(pi, tblDataLo);
+
+@@ -2894,7 +2900,7 @@ const u8 *wlc_phy_get_ofdm_rate_lookup(v
+
+ void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
+ {
+- if ((pi->sh->chip == BCM4313_CHIP_ID) &&
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4313) &&
+ (pi->sh->boardflags & BFL_FEM)) {
+ if (mode) {
+ u16 txant = 0;
+--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
+@@ -17895,6 +17895,8 @@ static u32 *wlc_phy_get_ipa_gaintbl_nphy
+ nphy_tpc_txgain_ipa_2g_2057rev7;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
++ if (pi->sh->chip == BCMA_CHIP_ID_BCM47162)
++ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
+ } else {
+@@ -19256,8 +19258,14 @@ static void wlc_phy_spurwar_nphy(struct
+ case 38:
+ case 102:
+ case 118:
+- nphy_adj_tone_id_buf[0] = 0;
+- nphy_adj_noise_var_buf[0] = 0x0;
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) &&
++ (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
++ nphy_adj_tone_id_buf[0] = 32;
++ nphy_adj_noise_var_buf[0] = 0x21f;
++ } else {
++ nphy_adj_tone_id_buf[0] = 0;
++ nphy_adj_noise_var_buf[0] = 0x0;
++ }
+ break;
+ case 134:
+ nphy_adj_tone_id_buf[0] = 32;
+@@ -19311,8 +19319,8 @@ void wlc_phy_init_nphy(struct brcms_phy
+ pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
+
+ if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
+- ((pi->sh->chippkg == BCM4717_PKG_ID) ||
+- (pi->sh->chippkg == BCM4718_PKG_ID))) {
++ ((pi->sh->chippkg == BCMA_PKG_ID_BCM4717) ||
++ (pi->sh->chippkg == BCMA_PKG_ID_BCM4718))) {
+ if ((pi->sh->boardflags & BFL_EXTLNA) &&
+ (CHSPEC_IS2G(pi->radio_chanspec)))
+ ai_cc_reg(pi->sh->sih,
+@@ -19320,6 +19328,10 @@ void wlc_phy_init_nphy(struct brcms_phy
+ 0x40, 0x40);
+ }
+
++ if ((!PHY_IPA(pi)) && (pi->sh->chip == BCMA_CHIP_ID_BCM5357))
++ si_pmu_chipcontrol(pi->sh->sih, 1, CCTRL5357_EXTPA,
++ CCTRL5357_EXTPA);
++
+ if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
+ CHSPEC_IS40(pi->radio_chanspec)) {
+
+@@ -20697,12 +20709,22 @@ wlc_phy_chanspec_radio2056_setup(struct
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
+ RADIO_2056_SYN, 0x1f);
+
+- write_radio_reg(pi,
+- RADIO_2056_SYN_PLL_LOOPFILTER4 |
+- RADIO_2056_SYN, 0xb);
+- write_radio_reg(pi,
+- RADIO_2056_SYN_PLL_CP2 |
+- RADIO_2056_SYN, 0x14);
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
++ (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
++ write_radio_reg(pi,
++ RADIO_2056_SYN_PLL_LOOPFILTER4 |
++ RADIO_2056_SYN, 0x14);
++ write_radio_reg(pi,
++ RADIO_2056_SYN_PLL_CP2 |
++ RADIO_2056_SYN, 0x00);
++ } else {
++ write_radio_reg(pi,
++ RADIO_2056_SYN_PLL_LOOPFILTER4 |
++ RADIO_2056_SYN, 0xb);
++ write_radio_reg(pi,
++ RADIO_2056_SYN_PLL_CP2 |
++ RADIO_2056_SYN, 0x14);
++ }
+ }
+ }
+
+@@ -20749,24 +20771,30 @@ wlc_phy_chanspec_radio2056_setup(struct
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PADG_IDAC, 0xcc);
+
+- bias = 0x25;
+- cascbias = 0x20;
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
++ (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
++ bias = 0x40;
++ cascbias = 0x45;
++ pag_boost_tune = 0x5;
++ pgag_boost_tune = 0x33;
++ padg_boost_tune = 0x77;
++ mixg_boost_tune = 0x55;
++ } else {
++ bias = 0x25;
++ cascbias = 0x20;
+
+- if ((pi->sh->chip ==
+- BCM43224_CHIP_ID)
+- || (pi->sh->chip ==
+- BCM43225_CHIP_ID)) {
+- if (pi->sh->chippkg ==
+- BCM43224_FAB_SMIC) {
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
++ pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
++ pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC) {
+ bias = 0x2a;
+ cascbias = 0x38;
+ }
+- }
+
+- pag_boost_tune = 0x4;
+- pgag_boost_tune = 0x03;
+- padg_boost_tune = 0x77;
+- mixg_boost_tune = 0x65;
++ pag_boost_tune = 0x4;
++ pgag_boost_tune = 0x03;
++ padg_boost_tune = 0x77;
++ mixg_boost_tune = 0x65;
++ }
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_IMAIN_STAT, bias);
+@@ -20865,11 +20893,10 @@ wlc_phy_chanspec_radio2056_setup(struct
+
+ cascbias = 0x30;
+
+- if ((pi->sh->chip == BCM43224_CHIP_ID) ||
+- (pi->sh->chip == BCM43225_CHIP_ID)) {
+- if (pi->sh->chippkg == BCM43224_FAB_SMIC)
+- cascbias = 0x35;
+- }
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
++ pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
++ pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC)
++ cascbias = 0x35;
+
+ pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
+
+@@ -21108,6 +21135,7 @@ wlc_phy_chanspec_nphy_setup(struct brcms
+ const struct nphy_sfo_cfg *ci)
+ {
+ u16 val;
++ struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
+
+ val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
+ if (CHSPEC_IS5G(chanspec) && !val) {
+@@ -21180,22 +21208,32 @@ wlc_phy_chanspec_nphy_setup(struct brcms
+ } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (val == 54)
+ spuravoid = 1;
+- } else {
+- if (pi->nphy_aband_spurwar_en &&
+- ((val == 38) || (val == 102)
+- || (val == 118)))
++ } else if (pi->nphy_aband_spurwar_en &&
++ ((val == 38) || (val == 102) || (val == 118))) {
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716)
++ && (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
++ spuravoid = 0;
++ } else {
+ spuravoid = 1;
++ }
+ }
+
+ if (pi->phy_spuravoid == SPURAVOID_FORCEON)
+ spuravoid = 1;
+
+- wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
+- si_pmu_spuravoid_pllupdate(pi->sh->sih, spuravoid);
+- wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
++ (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
++ bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
++ spuravoid);
++ } else {
++ wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
++ bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
++ spuravoid);
++ wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
++ }
+
+- if ((pi->sh->chip == BCM43224_CHIP_ID) ||
+- (pi->sh->chip == BCM43225_CHIP_ID)) {
++ if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) ||
++ (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
+ if (spuravoid == 1) {
+ bcma_write16(pi->d11core,
+ D11REGOFFS(tsf_clk_frac_l),
+@@ -21211,7 +21249,9 @@ wlc_phy_chanspec_nphy_setup(struct brcms
+ }
+ }
+
+- wlapi_bmac_core_phypll_reset(pi->sh->physhim);
++ if (!((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
++ (pi->sh->chip == BCMA_CHIP_ID_BCM47162)))
++ wlapi_bmac_core_phypll_reset(pi->sh->physhim);
+
+ mod_phy_reg(pi, 0x01, (0x1 << 15),
+ ((spuravoid > 0) ? (0x1 << 15) : 0));
+@@ -22173,9 +22213,15 @@ s16 wlc_phy_tempsense_nphy(struct brcms_
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
+ &auxADC_rssi_ctrlH_save);
+
+- radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
+- + 82 * (auxADC_Vl) - 28861 +
+- 128) / 256;
++ if (pi->sh->chip == BCMA_CHIP_ID_BCM5357) {
++ radio_temp[0] = (193 * (radio_temp[1] + radio_temp2[1])
++ + 88 * (auxADC_Vl) - 27111 +
++ 128) / 256;
++ } else {
++ radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
++ + 82 * (auxADC_Vl) - 28861 +
++ 128) / 256;
++ }
+
+ offset = (s16) pi->phy_tempsense_offset;
+
+@@ -24925,14 +24971,16 @@ wlc_phy_a2_nphy(struct brcms_phy *pi, st
+ if (txgains->useindex) {
+ phy_a4 = 15 - ((txgains->index) >> 3);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+- if (NREV_GE(pi->pubpi.phy_rev, 6))
++ if (NREV_GE(pi->pubpi.phy_rev, 6) &&
++ pi->sh->chip == BCMA_CHIP_ID_BCM47162) {
++ phy_a5 = 0x10f7 | (phy_a4 << 8);
++ } else if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ phy_a5 = 0x00f7 | (phy_a4 << 8);
+-
+- else
+- if (NREV_IS(pi->pubpi.phy_rev, 5))
++ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ phy_a5 = 0x10f7 | (phy_a4 << 8);
+- else
++ } else {
+ phy_a5 = 0x50f7 | (phy_a4 << 8);
++ }
+ } else {
+ phy_a5 = 0x70f7 | (phy_a4 << 8);
+ }
+--- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
+@@ -74,16 +74,6 @@
+ * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
+ * number to differentiate different PLLs controlled by the same PMU rev.
+ */
+-/* pllcontrol registers:
+- * ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
+- * p1div, p2div, _bypass_sdmod
+- */
+-#define PMU1_PLL0_PLLCTL0 0
+-#define PMU1_PLL0_PLLCTL1 1
+-#define PMU1_PLL0_PLLCTL2 2
+-#define PMU1_PLL0_PLLCTL3 3
+-#define PMU1_PLL0_PLLCTL4 4
+-#define PMU1_PLL0_PLLCTL5 5
+
+ /* pmu XtalFreqRatio */
+ #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
+@@ -108,118 +98,14 @@
+ #define RES4313_HT_AVAIL_RSRC 14
+ #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
+
+-/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
+-static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
+-{
+- u32 min_mask = 0, max_mask = 0;
+- uint rsrcs;
+-
+- /* # resources */
+- rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
+-
+- /* determine min/max rsrc masks */
+- switch (ai_get_chip_id(sih)) {
+- case BCM43224_CHIP_ID:
+- case BCM43225_CHIP_ID:
+- /* ??? */
+- break;
+-
+- case BCM4313_CHIP_ID:
+- min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
+- PMURES_BIT(RES4313_XTAL_PU_RSRC) |
+- PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
+- PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
+- max_mask = 0xffff;
+- break;
+- default:
+- break;
+- }
+-
+- *pmin = min_mask;
+- *pmax = max_mask;
+-}
+-
+-void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid)
+-{
+- u32 tmp = 0;
+- struct bcma_device *core;
+-
+- /* switch to chipc */
+- core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
+-
+- switch (ai_get_chip_id(sih)) {
+- case BCM43224_CHIP_ID:
+- case BCM43225_CHIP_ID:
+- if (spuravoid == 1) {
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL0);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x11500010);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL1);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x000C0C06);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL2);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x0F600a08);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL3);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x00000000);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL4);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x2001E920);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL5);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x88888815);
+- } else {
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL0);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x11100010);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL1);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x000c0c06);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL2);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x03000a08);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL3);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x00000000);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL4);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x200005c0);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
+- PMU1_PLL0_PLLCTL5);
+- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
+- 0x88888815);
+- }
+- tmp = 1 << 10;
+- break;
+-
+- default:
+- /* bail out */
+- return;
+- }
+-
+- bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
+-}
+-
+ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
+ {
+ uint delay = PMU_MAX_TRANSITION_DLY;
+
+ switch (ai_get_chip_id(sih)) {
+- case BCM43224_CHIP_ID:
+- case BCM43225_CHIP_ID:
+- case BCM4313_CHIP_ID:
++ case BCMA_CHIP_ID_BCM43224:
++ case BCMA_CHIP_ID_BCM43225:
++ case BCMA_CHIP_ID_BCM4313:
+ delay = 3700;
+ break;
+ default:
+@@ -270,9 +156,9 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
+ return clock;
+
+ switch (ai_get_chip_id(sih)) {
+- case BCM43224_CHIP_ID:
+- case BCM43225_CHIP_ID:
+- case BCM4313_CHIP_ID:
++ case BCMA_CHIP_ID_BCM43224:
++ case BCMA_CHIP_ID_BCM43225:
++ case BCMA_CHIP_ID_BCM4313:
+ /* always 20Mhz */
+ clock = 20000 * 1000;
+ break;
+@@ -283,51 +169,9 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
+ return clock;
+ }
+
+-/* initialize PMU */
+-void si_pmu_init(struct si_pub *sih)
+-{
+- struct bcma_device *core;
+-
+- /* select chipc */
+- core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
+-
+- if (ai_get_pmurev(sih) == 1)
+- bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
+- ~PCTL_NOILP_ON_WAIT);
+- else if (ai_get_pmurev(sih) >= 2)
+- bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
+-}
+-
+-/* initialize PMU resources */
+-void si_pmu_res_init(struct si_pub *sih)
+-{
+- struct bcma_device *core;
+- u32 min_mask = 0, max_mask = 0;
+-
+- /* select to chipc */
+- core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
+-
+- /* Determine min/max rsrc masks */
+- si_pmu_res_masks(sih, &min_mask, &max_mask);
+-
+- /* It is required to program max_mask first and then min_mask */
+-
+- /* Program max resource mask */
+-
+- if (max_mask)
+- bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
+-
+- /* Program min resource mask */
+-
+- if (min_mask)
+- bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
+-
+- /* Add some delay; allow resources to come up and settle. */
+- mdelay(2);
+-}
+-
+ u32 si_pmu_measure_alpclk(struct si_pub *sih)
+ {
++ struct si_info *sii = container_of(sih, struct si_info, pub);
+ struct bcma_device *core;
+ u32 alp_khz;
+
+@@ -335,7 +179,7 @@ u32 si_pmu_measure_alpclk(struct si_pub
+ return 0;
+
+ /* Remember original core before switch to chipc */
+- core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
++ core = sii->icbus->drv_cc.core;
+
+ if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
+ u32 ilp_ctr, alp_hz;
+--- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.h
++++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.h
+@@ -26,10 +26,7 @@ extern u32 si_pmu_chipcontrol(struct si_
+ extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
+ extern u32 si_pmu_alp_clock(struct si_pub *sih);
+ extern void si_pmu_pllupd(struct si_pub *sih);
+-extern void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid);
+ extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
+-extern void si_pmu_init(struct si_pub *sih);
+-extern void si_pmu_res_init(struct si_pub *sih);
+ extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
+
+ #endif /* _BRCM_PMU_H_ */
+--- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
++++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
+@@ -311,7 +311,7 @@ extern uint brcms_c_detach(struct brcms_
+ extern int brcms_c_up(struct brcms_c_info *wlc);
+ extern uint brcms_c_down(struct brcms_c_info *wlc);
+
+-extern bool brcms_c_chipmatch(u16 vendor, u16 device);
++extern bool brcms_c_chipmatch(struct bcma_device *core);
+ extern void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx);
+ extern void brcms_c_reset(struct brcms_c_info *wlc);
+
+--- a/drivers/net/wireless/brcm80211/include/soc.h
++++ b/drivers/net/wireless/brcm80211/include/soc.h
+@@ -19,68 +19,6 @@
+
+ #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
+
+-/* core codes */
+-#define NODEV_CORE_ID 0x700 /* Invalid coreid */
+-#define CC_CORE_ID 0x800 /* chipcommon core */
+-#define ILINE20_CORE_ID 0x801 /* iline20 core */
+-#define SRAM_CORE_ID 0x802 /* sram core */
+-#define SDRAM_CORE_ID 0x803 /* sdram core */
+-#define PCI_CORE_ID 0x804 /* pci core */
+-#define MIPS_CORE_ID 0x805 /* mips core */
+-#define ENET_CORE_ID 0x806 /* enet mac core */
+-#define CODEC_CORE_ID 0x807 /* v90 codec core */
+-#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
+-#define ADSL_CORE_ID 0x809 /* ADSL core */
+-#define ILINE100_CORE_ID 0x80a /* iline100 core */
+-#define IPSEC_CORE_ID 0x80b /* ipsec core */
+-#define UTOPIA_CORE_ID 0x80c /* utopia core */
+-#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
+-#define SOCRAM_CORE_ID 0x80e /* internal memory core */
+-#define MEMC_CORE_ID 0x80f /* memc sdram core */
+-#define OFDM_CORE_ID 0x810 /* OFDM phy core */
+-#define EXTIF_CORE_ID 0x811 /* external interface core */
+-#define D11_CORE_ID 0x812 /* 802.11 MAC core */
+-#define APHY_CORE_ID 0x813 /* 802.11a phy core */
+-#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
+-#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
+-#define MIPS33_CORE_ID 0x816 /* mips3302 core */
+-#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
+-#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
+-#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
+-#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
+-#define SDIOH_CORE_ID 0x81b /* sdio host core */
+-#define ROBO_CORE_ID 0x81c /* roboswitch core */
+-#define ATA100_CORE_ID 0x81d /* parallel ATA core */
+-#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
+-#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
+-#define PCIE_CORE_ID 0x820 /* pci express core */
+-#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
+-#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
+-#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
+-#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
+-#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
+-#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
+-#define PMU_CORE_ID 0x827 /* PMU core */
+-#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
+-#define SDIOD_CORE_ID 0x829 /* SDIO device core */
+-#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
+-#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
+-#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
+-#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
+-#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
+-#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
+-#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
+-#define SC_CORE_ID 0x831 /* shared common core */
+-#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
+-#define SPIH_CORE_ID 0x833 /* SPI host core */
+-#define I2S_CORE_ID 0x834 /* I2S core */
+-#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
+-#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
+-#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
+-#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
+- * maps all unused address ranges
+- */
+-
+ /* Common core control flags */
+ #define SICF_BIST_EN 0x8000
+ #define SICF_PME_EN 0x4000
projects / openwrt / staging / hauke.git / commitdiff