drm/radeon: use lower_32_bits where appropriate

Replace occurrences of "v & 0xffffffff" with lower_32_bits(v)
when it's next to an upper_32_bits(v). Also remove unnecessary
"upper_32_bits(v) & 0xffffffff" code snippets.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 69a00d64716e0b5f9267c7f9bb22af608a02297c..5e0a41a8e7930544ced2b968ce1faffbf56a9a9b 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3698,7 +3698,7 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
        unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
 
        radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
 
        return true;
@@ -3818,7 +3818,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
                        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
                        radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
                        radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-                       radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+                       radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
                        radeon_ring_write(ring, next_rptr);
                }
 

diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 1347162ca1a4265854b8a8152a30657433db4c3e..8e9d0f1d858ef56d4038ab1361f339a2ba593f8f 100644 (file)
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -141,7 +141,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
                next_rptr += 4;
                radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
                radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-               radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+               radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
                radeon_ring_write(ring, 1); /* number of DWs to follow */
                radeon_ring_write(ring, next_rptr);
        }
@@ -151,7 +151,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
                radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
        radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
-       radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
+       radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
        radeon_ring_write(ring, ib->length_dw);
 
 }
@@ -203,8 +203,8 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 
        /* write the fence */
        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
-       radeon_ring_write(ring, addr & 0xffffffff);
-       radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
+       radeon_ring_write(ring, upper_32_bits(addr));
        radeon_ring_write(ring, fence->seq);
        /* generate an interrupt */
        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
@@ -233,7 +233,7 @@ bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 
        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
        radeon_ring_write(ring, addr & 0xfffffff8);
-       radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+       radeon_ring_write(ring, upper_32_bits(addr));
 
        return true;
 }
@@ -551,10 +551,10 @@ int cik_copy_dma(struct radeon_device *rdev,
                radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
                radeon_ring_write(ring, cur_size_in_bytes);
                radeon_ring_write(ring, 0); /* src/dst endian swap */
-               radeon_ring_write(ring, src_offset & 0xffffffff);
-               radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
-               radeon_ring_write(ring, dst_offset & 0xffffffff);
-               radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(src_offset));
+               radeon_ring_write(ring, upper_32_bits(src_offset));
+               radeon_ring_write(ring, lower_32_bits(dst_offset));
+               radeon_ring_write(ring, upper_32_bits(dst_offset));
                src_offset += cur_size_in_bytes;
                dst_offset += cur_size_in_bytes;
        }
@@ -605,7 +605,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
        }
        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
        radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
-       radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);
+       radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
        radeon_ring_write(ring, 1); /* number of DWs to follow */
        radeon_ring_write(ring, 0xDEADBEEF);
        radeon_ring_unlock_commit(rdev, ring);
@@ -660,7 +660,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 
        ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
        ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
-       ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;
+       ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
        ib.ptr[3] = 1;
        ib.ptr[4] = 0xDEADBEEF;
        ib.length_dw = 5;
@@ -752,9 +752,9 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
                        ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
                        ib->ptr[ib->length_dw++] = bytes;
                        ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
-                       ib->ptr[ib->length_dw++] = src & 0xffffffff;
+                       ib->ptr[ib->length_dw++] = lower_32_bits(src);
                        ib->ptr[ib->length_dw++] = upper_32_bits(src);
-                       ib->ptr[ib->length_dw++] = pe & 0xffffffff;
+                       ib->ptr[ib->length_dw++] = lower_32_bits(pe);
                        ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 
                        pe += bytes;

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 1d3209ffbbdc354af7666a92fb3faf3b89db6b0c..8c3fbb1d412be3bc5f696ba614b39a453e7150ef 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1346,7 +1346,7 @@ void cayman_fence_ring_emit(struct radeon_device *rdev,
        /* EVENT_WRITE_EOP - flush caches, send int */
        radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
        radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
        radeon_ring_write(ring, fence->seq);
        radeon_ring_write(ring, 0);

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c75881223d18c5f36d5b4bfebd015fa06eee5ba0..c2ff17cebd91d38398abf0501e601e33fd5ae12d 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2724,7 +2724,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
                /* EVENT_WRITE_EOP - flush caches, send int */
                radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
                radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
-               radeon_ring_write(ring, addr & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(addr));
                radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
                radeon_ring_write(ring, fence->seq);
                radeon_ring_write(ring, 0);
@@ -2763,7 +2763,7 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
                sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
 
        radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
 
        return true;
@@ -2824,9 +2824,9 @@ int r600_copy_cpdma(struct radeon_device *rdev,
                if (size_in_bytes == 0)
                        tmp |= PACKET3_CP_DMA_CP_SYNC;
                radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
-               radeon_ring_write(ring, src_offset & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(src_offset));
                radeon_ring_write(ring, tmp);
-               radeon_ring_write(ring, dst_offset & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(dst_offset));
                radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
                radeon_ring_write(ring, cur_size_in_bytes);
                src_offset += cur_size_in_bytes;

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d64ef9115b69e27a6eaab286966da1d14876cece..85d030ecebae84f9058b6936fa37793a0c727a6a 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3186,7 +3186,7 @@ void si_fence_ring_emit(struct radeon_device *rdev,
        /* EVENT_WRITE_EOP - flush caches, send int */
        radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
        radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
        radeon_ring_write(ring, fence->seq);
        radeon_ring_write(ring, 0);
@@ -3219,7 +3219,7 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
                        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
                        radeon_ring_write(ring, (1 << 8));
                        radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-                       radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+                       radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
                        radeon_ring_write(ring, next_rptr);
                }
 

diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index 9a660f861d2cc331c466aff8411900b17737f67a..e24c94b6d14d133dd66acfc72593cc5d5a6eb2c7 100644 (file)
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -88,8 +88,8 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
 
                        ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
                                                              1, 0, 0, bytes);
-                       ib->ptr[ib->length_dw++] = pe & 0xffffffff;
-                       ib->ptr[ib->length_dw++] = src & 0xffffffff;
+                       ib->ptr[ib->length_dw++] = lower_32_bits(pe);
+                       ib->ptr[ib->length_dw++] = lower_32_bits(src);
                        ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
                        ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
 
@@ -220,8 +220,8 @@ int si_copy_dma(struct radeon_device *rdev,
                        cur_size_in_bytes = 0xFFFFF;
                size_in_bytes -= cur_size_in_bytes;
                radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
-               radeon_ring_write(ring, dst_offset & 0xffffffff);
-               radeon_ring_write(ring, src_offset & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(dst_offset));
+               radeon_ring_write(ring, lower_32_bits(src_offset));
                radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
                radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
                src_offset += cur_size_in_bytes;

diff --git a/drivers/gpu/drm/radeon/uvd_v2_2.c b/drivers/gpu/drm/radeon/uvd_v2_2.c
index d1771004cb52ecee46ae22dc7665bd54adb477b6..8bfdadd5659881d6a47b10ff888592c96417ebee 100644 (file)
--- a/drivers/gpu/drm/radeon/uvd_v2_2.c
+++ b/drivers/gpu/drm/radeon/uvd_v2_2.c
@@ -45,7 +45,7 @@ void uvd_v2_2_fence_emit(struct radeon_device *rdev,
        radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
        radeon_ring_write(ring, fence->seq);
        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
        radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));