--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
+ * Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
+ */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+
+
+/ {
+ model = "Zyxel NBG7815";
+ compatible = "zyxel,nbg7815", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ /* Alias as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp1;
+ label-mac-device = &dp1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsbl";
+ reg = <0x480000 0xc0000>;
+ read-only;
+ };
+
+ partition@540000 {
+ label = "0:appsbl_1";
+ reg = <0x540000 0xc0000>;
+ read-only;
+ };
+
+ partition@600000 {
+ compatible = "u-boot,env";
+ label = "0:appsblenv";
+ reg = <0x600000 0x10000>;
+
+ macaddr_lan: ethaddr {
+ };
+ };
+
+ partition@610000 {
+ label = "0:art";
+ reg = <0x610000 0x40000>;
+ read-only;
+ };
+
+ partition@650000 {
+ label = "0:ethphyfw";
+ reg = <0x650000 0x80000>;
+ read-only;
+ };
+
+ partition@6d0000 {
+ label = "0:crt";
+ reg = <0x6d0000 0x10000>;
+ read-only;
+ };
+
+ partition@6e0000 {
+ label = "dual_flag";
+ reg = <0x6e0000 0x10000>;
+ };
+
+ partition@6f0000 {
+ label = "reserved";
+ reg = <0x6f0000 0x110000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_2: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_3: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_4: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@4{
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ };
+
+ aqr113c: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x3e>;
+ switch_wan_bmp = <0x40>;
+ switch_mac_mode = <0x0>;
+ switch_mac_mode1 = <0xf>;
+ switch_mac_mode2 = <0xd>;
+ bm_tick_mode = <0>;
+ tm_tick_mode = <0>;
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@4 {
+ port_id = <5>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+
+ port@5 {
+ port_id = <6>;
+ ethernet-phy-ieee802.3-c45;
+ phy_address = <8>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+ mac-address-increment = <1>;
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&aqr113c>;
+ label = "10g";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address-ascii";
+};
+
+&blsp1_i2c2 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ tmp103@70 {
+ compatible = "ti,tmp103";
+ reg = <0x70>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+ /* unstable, problem with the hs400 > h200 speed switch */
+ /delete-property/ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ vqmmc-supply = <&l11>;
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
+};
projects / openwrt / staging / stintel.git / commitdiff