ar71xx: fix ethernet device registration for QCA9558

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 34853

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 7975464333a930c0ad73f36c35873307e4a5c8ec..043300c18802683561c55fccf6a8dcbfb0b23d83 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -355,6 +355,26 @@ static void ar934x_set_speed_ge0(int speed)
        iounmap(base);
 }
 
+static void qca955x_set_speed_xmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(0, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
+       iounmap(base);
+}
+
+static void qca955x_set_speed_sgmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(1, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
+       iounmap(base);
+}
+
 static void ath79_set_speed_dummy(int speed)
 {
 }
@@ -905,7 +925,6 @@ void __init ath79_register_eth(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
-       case ATH79_SOC_QCA9558:
                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;
@@ -934,6 +953,29 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 
+       case ATH79_SOC_QCA9558:
+               if (id == 0) {
+                       pdata->reset_bit = QCA955X_RESET_GE0_MAC |
+                                          QCA955X_RESET_GE0_MDIO;
+                       pdata->set_speed = qca955x_set_speed_xmii;
+               } else {
+                       pdata->reset_bit = QCA955X_RESET_GE1_MAC |
+                                          QCA955X_RESET_GE1_MDIO;
+                       pdata->set_speed = qca955x_set_speed_sgmii;
+               }
+
+               pdata->ddr_flush = ath79_ddr_no_flush;
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
        default:
                BUG();
        }

diff --git a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
index 01852482ee64ae18df2d9eb5d713b8f9640eb93b..407de3600826ad634a63b5fa0c46640efff97482 100644 (file)
--- a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
@@ -93,7 +93,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -252,6 +278,8 @@
+@@ -252,9 +278,13 @@
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
  
@@ -102,7 +102,12 @@
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08
-@@ -378,16 +406,50 @@
++#define QCA955X_PLL_ETH_XMII_CONTROL_REG      0x28
++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG     0x48
+ 
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
+@@ -378,16 +408,83 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
@@ -147,13 +152,46 @@
 +#define AR934X_RESET_LUT              BIT(2)
 +#define AR934X_RESET_MBOX             BIT(1)
 +#define AR934X_RESET_I2S              BIT(0)
++
++#define QCA955X_RESET_HOST            BIT(31)
++#define QCA955X_RESET_SLIC            BIT(30)
++#define QCA955X_RESET_HDMA            BIT(29)
++#define QCA955X_RESET_EXTERNAL                BIT(28)
++#define QCA955X_RESET_RTC             BIT(27)
++#define QCA955X_RESET_PCIE_EP_INT     BIT(26)
++#define QCA955X_RESET_CHKSUM_ACC      BIT(25)
++#define QCA955X_RESET_FULL_CHIP               BIT(24)
++#define QCA955X_RESET_GE1_MDIO                BIT(23)
++#define QCA955X_RESET_GE0_MDIO                BIT(22)
++#define QCA955X_RESET_CPU_NMI         BIT(21)
++#define QCA955X_RESET_CPU_COLD                BIT(20)
++#define QCA955X_RESET_HOST_RESET_INT  BIT(19)
++#define QCA955X_RESET_PCIE_EP         BIT(18)
++#define QCA955X_RESET_UART1           BIT(17)
++#define QCA955X_RESET_DDR             BIT(16)
++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA955X_RESET_NANDF           BIT(14)
++#define QCA955X_RESET_GE1_MAC         BIT(13)
++#define QCA955X_RESET_SGMII_ANALOG    BIT(12)
++#define QCA955X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA955X_RESET_HOST_DMA_INT    BIT(10)
++#define QCA955X_RESET_GE0_MAC         BIT(9)
++#define QCA955X_RESET_SGMII           BIT(8)
++#define QCA955X_RESET_PCIE_PHY                BIT(7)
++#define QCA955X_RESET_PCIE            BIT(6)
++#define QCA955X_RESET_USB_HOST                BIT(5)
++#define QCA955X_RESET_USB_PHY         BIT(4)
++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
++#define QCA955X_RESET_LUT             BIT(2)
++#define QCA955X_RESET_MBOX            BIT(1)
++#define QCA955X_RESET_I2S             BIT(0)
  
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -528,6 +590,12 @@
+@@ -528,6 +625,12 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
@@ -166,7 +204,7 @@
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR71XX_GPIO_COUNT             16
-@@ -559,4 +627,133 @@
+@@ -559,4 +662,133 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7