Add support to change xlat_tables to non-cacheable

This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.

Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4
Signed-off-by: Summer Qin <summer.qin@arm.com>

diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index 1f4ae6d0c86f879e2669713c2c8ee15c36683f87..3105d7aaee5c31200d5d00a0d3dea4417607e44c 100644 (file)
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -135,4 +135,10 @@
  */
 #define DISABLE_DCACHE                 (1 << 0)
 
+/*
+ * This flag marks the translation tables are Non-cacheable for MMU accesses.
+ * If the flag is not specified, by default the tables are cacheable.
+ */
+#define XLAT_TABLE_NC                  (1 << 1)
+
 #endif /* __XLAT_TABLES_DEFS_H__ */

diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index e8408da89c094968d39c1b974c76c8dd50619f4e..316a60e70e6dab33d78ce36171d454e8552d9ef6 100644 (file)
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -130,13 +130,21 @@ void enable_mmu_secure(unsigned int flags)
        tlbiall();
 
        /*
-        * Set TTBCR bits as well. Set TTBR0 table properties as Inner
-        * & outer WBWA & shareable. Disable TTBR1.
+        * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
         */
-       ttbcr = TTBCR_EAE_BIT |
-               TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
-               TTBCR_RGN0_INNER_WBA |
-               (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       if (flags & XLAT_TABLE_NC) {
+               /* Inner & outer non-cacheable non-shareable. */
+               ttbcr = TTBCR_EAE_BIT |
+                       TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
+                       TTBCR_RGN0_INNER_NC |
+                       (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       } else {
+               /* Inner & outer WBWA & shareable. */
+               ttbcr = TTBCR_EAE_BIT |
+                       TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
+                       TTBCR_RGN0_INNER_WBA |
+                       (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       }
        ttbcr |= TTBCR_EPD1_BIT;
        write_ttbcr(ttbcr);
 

diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index af12b9f1966f25255607672e3c2ddff580cd02e0..ecb120220cf4c11f7a71976f9f20a1cf518fd935 100644 (file)
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -192,11 +192,18 @@ void init_xlat_tables(void)
                _tlbi_fct();                                            \
                                                                        \
                /* Set TCR bits as well. */                             \
-               /* Inner & outer WBWA & shareable. */                   \
                /* Set T0SZ to (64 - width of virtual address space) */ \
-               tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |      \
-                       TCR_RGN_INNER_WBA |                             \
-                       (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               if (flags & XLAT_TABLE_NC) {                            \
+                       /* Inner & outer non-cacheable non-shareable. */\
+                       tcr = TCR_SH_NON_SHAREABLE |                    \
+                               TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |   \
+                               (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               } else {                                                \
+                       /* Inner & outer WBWA & shareable. */           \
+                       tcr = TCR_SH_INNER_SHAREABLE |                  \
+                               TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
+                               (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               }                                                       \
                tcr |= _tcr_extra;                                      \
                write_tcr_el##_el(tcr);                                 \
                                                                        \

diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 7de90304b546160f673f4c2dff41dbb66d33f87f..ba0e53d6fdc864ce1cdc3fa35ae77cc7a12fcecb 100644 (file)
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -122,13 +122,21 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
        write_mair0(mair0);
 
        /*
-        * Set TTBCR bits as well. Set TTBR0 table properties as Inner
-        * & outer WBWA & shareable. Disable TTBR1.
+        * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
         */
-       ttbcr = TTBCR_EAE_BIT |
-               TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
-               TTBCR_RGN0_INNER_WBA |
-               (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       if (flags & XLAT_TABLE_NC) {
+               /* Inner & outer non-cacheable non-shareable. */
+               ttbcr = TTBCR_EAE_BIT |
+                       TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
+                       TTBCR_RGN0_INNER_NC |
+                       (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       } else {
+               /* Inner & outer WBWA & shareable. */
+               ttbcr = TTBCR_EAE_BIT |
+                       TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
+                       TTBCR_RGN0_INNER_WBA |
+                       (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+       }
        ttbcr |= TTBCR_EPD1_BIT;
        write_ttbcr(ttbcr);
 

diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 235fa4453ecb8efc9b028148b185215d62bd0018..575ac71cecc8da86fe65354ca754aede1fe1dd9f 100644 (file)
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -201,11 +201,18 @@ void init_xlat_tables_arch(unsigned long long max_pa)
                write_mair_el##_el(mair);                               \
                                                                        \
                /* Set TCR bits as well. */                             \
-               /* Inner & outer WBWA & shareable. */                   \
                /* Set T0SZ to (64 - width of virtual address space) */ \
-               tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |      \
-                       TCR_RGN_INNER_WBA |                             \
-                       (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               if (flags & XLAT_TABLE_NC) {                            \
+                       /* Inner & outer non-cacheable non-shareable. */\
+                       tcr = TCR_SH_NON_SHAREABLE |                    \
+                               TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |   \
+                               (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               } else {                                                \
+                       /* Inner & outer WBWA & shareable. */           \
+                       tcr = TCR_SH_INNER_SHAREABLE |                  \
+                               TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
+                               (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+               }                                                       \
                tcr |= _tcr_extra;                                      \
                write_tcr_el##_el(tcr);                                 \
                                                                        \