powerpc/82xx: add SPI support for mgcoge
authorHolger Brunck <holger.brunck@keymile.com>
Tue, 8 May 2012 13:57:22 +0000 (15:57 +0200)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 10 Jul 2012 12:07:20 +0000 (07:07 -0500)
Add spi support for mgcoge into the platform code and the dts
file. Additionaly SPIDEV is switched on in the defconfig and the
updates for the newer kernel version are committed. The SPI
interface is used to drive the Maxim DS3106 clock chip.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/mgcoge.dts
arch/powerpc/configs/mgcoge_defconfig
arch/powerpc/platforms/82xx/km82xx.c

index ededaf5ac015e78b2fc269b4151b919ce5552497..d72fb5e219d08c2b67423449d85012c518733d23 100644 (file)
                                interrupt-parent = <&PIC>;
                                usb-clock = <5>;
                        };
+                       spi@11aa0 {
+                               cell-index = <0>;
+                               compatible = "fsl,spi", "fsl,cpm2-spi";
+                               reg = <0x11a80 0x40 0x89fc 0x2>;
+                               interrupts = <2 8>;
+                               interrupt-parent = <&PIC>;
+                               gpios = < &cpm2_pio_d 19 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               ds3106@1 {
+                                       compatible = "gen,spidev";
+                                       reg = <0>;
+                                       spi-max-frequency = <8000000>;
+                               };
+                       };
+
+               };
+
+               cpm2_pio_d: gpio-controller@10d60 {
+                       #gpio-cells = <2>;
+                       compatible = "fsl,cpm2-pario-bank";
+                       reg = <0x10d60 0x14>;
+                       gpio-controller;
                };
 
                cpm2_pio_c: gpio-controller@10d40 {
index 0d36b0e1e2681134f86d50934c1413f46b27f71b..8fa84f156ef3f28eea3a45c6f02df28f55b5be86 100644 (file)
@@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_SPARSE_IRQ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -12,6 +11,7 @@ CONFIG_KALLSYMS_ALL=y
 # CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
+CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_CFQ is not set
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_82xx=y
@@ -49,12 +49,9 @@ CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_FS_ENET=y
 CONFIG_FS_ENET_MDIO_FCC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+CONFIG_FIXED_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
@@ -64,6 +61,8 @@ CONFIG_SERIAL_CPM_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_CPM=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_SPI=y
 # CONFIG_HWMON is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FSL_USB2=y
@@ -80,8 +79,6 @@ CONFIG_SQUASHFS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
@@ -90,7 +87,6 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_BDI_SWITCH=y
 CONFIG_CRYPTO_ECB=y
 CONFIG_CRYPTO_PCBC=y
index 3661bcdc326a6551b0e0a11c8d964e4b0597a619..cf964e19573a15b8d8c3f9f2c33f0079f146f290 100644 (file)
@@ -128,6 +128,11 @@ static __initdata struct cpm_pin km82xx_pins[] = {
        {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */
        {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */
        {3, 25, CPM_PIN_INPUT  | CPM_PIN_PRIMARY}, /* RXD */
+
+       /* SPI */
+       {3, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MISO PD16 */
+       {3, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MOSI PD17 */
+       {3, 18, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_CLK PD18 */
 };
 
 static void __init init_ioports(void)