fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
  and now two.

- This patch updates the value of open power switches from
  0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index 1b68d0767eaa7fc550cab781da98a8bb3ff77e00..285441691f59de0d6fbebaf2d6363051d4f2f167 100644 (file)
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -79,7 +79,7 @@ enum CPU_ID {
        #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET           1
        #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET      0
 #else
-#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET          0
+       #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET           0
        #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET      31
 #endif
 
@@ -106,7 +106,7 @@ enum CPU_ID {
 #define AP807_PWRC_LDO_CR0_OFFSET              16
 #define AP807_PWRC_LDO_CR0_MASK                        \
                        (0xff << AP807_PWRC_LDO_CR0_OFFSET)
-#define AP807_PWRC_LDO_CR0_VAL                 0xfd
+#define AP807_PWRC_LDO_CR0_VAL                 0xfc
 
 /*
  * Power down CPU: