pinctrl: mvebu: armada-39x: align NAND pin naming

All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.

It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.

While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
index 34af69ef321d7dec6ba6f279daf2e3a3acb67e6c..b6bd9cc09af8db35d87f035ce2cf4f05807b1933 100644 (file)
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
@@ -55,9 +55,9 @@ mpp37 37      gpio, sd0(d3), dev(ad8), ge(rxclk)
 mpp38  38      gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1)
 mpp39  39      gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2)
 mpp40  40      gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3)
-mpp41  41      gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl)
+mpp41  41      gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl)
 mpp42  42      gpio, ua1(txd), ua0(rts), dev(ad7)
-mpp43  43      gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1)
+mpp43  43      gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
 mpp44  44      gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk)
 mpp45  45      gpio, ref(clk), pcie0(rstout), ua1(rxd)
 mpp46  46      gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
index a5e362714df8f77d0a480e09a4ce71640cc2c798..de91b35986533cf0772020634d1450f1e454ae2a 100644 (file)
--- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
@@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
                 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(4, "spi1",    "cs3",      V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(5, "dev",     "burst/last", V_88F6920_PLUS),
-                MPP_VAR_FUNCTION(6, "nd",      "rbn0",     V_88F6920_PLUS),
+                MPP_VAR_FUNCTION(6, "nand",    "rb0",      V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(8, "ge",      "rxctl",    V_88F6920_PLUS)),
        MPP_MODE(42,
                 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
@@ -255,7 +255,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
                 MPP_VAR_FUNCTION(3, "dram",    "deccerr",  V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(4, "spi1",    "cs2",      V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(5, "dev",     "clkout",   V_88F6920_PLUS),
-                MPP_VAR_FUNCTION(6, "nd",      "rbn1",     V_88F6920_PLUS)),
+                MPP_VAR_FUNCTION(6, "nand",    "rb1",      V_88F6920_PLUS)),
        MPP_MODE(44,
                 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
                 MPP_VAR_FUNCTION(1, "sata0",   "prsnt",    V_88F6928),