help
Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
-config USB_MUSB_DEBUG
- depends on USB_MUSB_HDRC
- bool "Enable debugging messages"
- default n
- help
- This enables musb debugging. To set the logging level use the debug
- module parameter. Starting at level 3, per-transfer (urb, usb_request,
- packet, or dma transfer) tracing may kick in.
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
-ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
-
obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
musb_hdrc-y := musb_core.o
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "Poll devctl %02x (%s)\n", devctl,
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
- DBG(4, "%s active, deleting timer\n",
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
- DBG(4, "Longer idle timer already pending, ignoring...\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
- DBG(4, "%s inactive, starting idle timer for %u ms\n",
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
otg_state_string(musb->xceiv->state),
jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
}
/* NOTE: this must complete power-on within 100 ms. */
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
musb_writew(epio, MUSB_TXCOUNT, len);
- DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
+ dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
hw_ep->epnum, fifo, len, src, epio);
dump_fifo_data(src, len);
*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
}
}
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', hw_ep->epnum, fifo, len, dst);
dump_fifo_data(dst, len);
}
break;
default:
- DBG(1, "%s state not handled\n",
+ dev_dbg(musb->controller, "%s state not handled\n",
otg_state_string(musb->xceiv->state));
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
- DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state));
+ dev_dbg(musb->controller, "state is %s\n",
+ otg_state_string(musb->xceiv->state));
}
static void bfin_musb_enable(struct musb *musb)
value = !value;
gpio_set_value(musb->config->gpio_vrsel, value);
- DBG(1, "VBUS %s, devctl %02x "
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
DAVINCI_DMA_ALL_CHANNELS_ENABLE);
- DBG(1, "Tearing down RX and TX Channels\n");
+ dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
/* FIXME restructure of txdma to use bds like rxdma */
controller->tx[i].last_processed = NULL;
*/
if (transmit) {
if (index >= ARRAY_SIZE(controller->tx)) {
- DBG(1, "no %cX%d CPPI channel\n", 'T', index);
+ dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
return NULL;
}
cppi_ch = controller->tx + index;
} else {
if (index >= ARRAY_SIZE(controller->rx)) {
- DBG(1, "no %cX%d CPPI channel\n", 'R', index);
+ dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
return NULL;
}
cppi_ch = controller->rx + index;
* with the other DMA engine too
*/
if (cppi_ch->hw_ep)
- DBG(1, "re-allocating DMA%d %cX channel %p\n",
+ dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
index, transmit ? 'T' : 'R', cppi_ch);
cppi_ch->hw_ep = ep;
cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
cppi_ch->channel.max_len = 0x7fffffff;
- DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
+ dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
return &cppi_ch->channel;
}
c = container_of(channel, struct cppi_channel, channel);
tibase = c->controller->tibase;
if (!c->hw_ep)
- DBG(1, "releasing idle DMA channel %p\n", c);
+ dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
else if (!c->transmit)
core_rxirq_enable(tibase, c->index + 1);
length = min(n_bds * maxpacket, length);
}
- DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
+ dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
tx->index,
maxpacket,
rndis ? "rndis" : "transparent",
bd->hw_options |= CPPI_ZERO_SET;
}
- DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
+ dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
length = min(n_bds * maxpacket, length);
- DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
+ dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
"dma 0x%llx len %u %u/%u\n",
rx->index, maxpacket,
onepacket
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
& 0xffff;
if (i < (2 + n_bds)) {
- DBG(2, "bufcnt%d underrun - %d (for %d)\n",
+ dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
rx->index, i, n_bds);
musb_writel(tibase,
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
/* WARN_ON(1); */
break;
case MUSB_DMA_STATUS_UNKNOWN:
- DBG(1, "%cX DMA%d not allocated!\n",
+ dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
cppi_ch->transmit ? 'T' : 'R',
cppi_ch->index);
/* FALLTHROUGH */
if (!completed && (bd->hw_options & CPPI_OWN_SET))
break;
- DBG(5, "C/RXBD %llx: nxt %08x buf %08x "
+ dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
"off.len %08x opt.len %08x (%d)\n",
(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options,
* CPPI ignores those BDs even though OWN is still set.
*/
completed = true;
- DBG(3, "rx short %d/%d (%d)\n",
+ dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
len, bd->buflen,
rx->channel.actual_len);
}
musb_ep_select(cppi->mregs, rx->index + 1);
csr = musb_readw(regs, MUSB_RXCSR);
if (csr & MUSB_RXCSR_DMAENAB) {
- DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n",
+ dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
rx->index,
rx->head, rx->tail,
rx->last_processed
return IRQ_NONE;
}
- DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
+ dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
/* process TX channels */
for (index = 0; tx; tx = tx >> 1, index++) {
* that needs to be acknowledged.
*/
if (NULL == bd) {
- DBG(1, "null BD\n");
+ dev_dbg(musb->controller, "null BD\n");
musb_writel(&tx_ram->tx_complete, 0, 0);
continue;
}
if (bd->hw_options & CPPI_OWN_SET)
break;
- DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n",
+ dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "Poll devctl %02x (%s)\n", devctl,
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
- DBG(4, "%s active, deleting timer\n",
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
- DBG(4, "Longer idle timer already pending, ignoring...\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
- DBG(4, "%s inactive, starting idle timer for %u ms\n",
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
otg_state_string(musb->xceiv->state),
jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
goto eoi;
musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
- DBG(4, "USB IRQ %08x\n", status);
+ dev_dbg(musb->controller, "USB IRQ %08x\n", status);
musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
break;
#endif
default:
- DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
+ dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
}
__raw_writel(cfgchip2, CFGCHIP2);
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "poll devctl %02x (%s)\n", devctl,
+ dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
/* ack and handle non-CPPI interrupts */
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
- DBG(4, "IRQ %08x\n", tmp);
+ dev_dbg(musb->controller, "IRQ %08x\n", tmp);
musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
>> DAVINCI_USB_RXINT_SHIFT;
* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
*/
davinci_musb_source_power(musb, drvvbus, 0);
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
break;
if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
warn = devctl & MUSB_DEVCTL_VBUS;
- DBG(1, "VBUS %d\n",
+ dev_dbg(musb->controller, "VBUS %d\n",
warn >> MUSB_DEVCTL_VBUS_SHIFT);
}
msleep(1000);
/* in OTG mode, another host might be connected */
if (devctl & MUSB_DEVCTL_VBUS)
- DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
+ dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
}
phy_off();
#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
-unsigned musb_debug;
-module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
-
#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
& MUSB_ULPI_REG_CMPLT)) {
i++;
- if (i == 10000) {
- DBG(3, "ULPI read timed out\n");
+ if (i == 10000)
return -ETIMEDOUT;
- }
}
r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
& MUSB_ULPI_REG_CMPLT)) {
i++;
- if (i == 10000) {
- DBG(3, "ULPI write timed out\n");
+ if (i == 10000)
return -ETIMEDOUT;
- }
}
r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
*/
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
prefetch((u8 *)src);
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'T', hw_ep->epnum, fifo, len, src);
/* we can't assume unaligned reads work */
*/
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', hw_ep->epnum, fifo, len, dst);
/* we can't assume unaligned writes work */
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
+ dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
musb_g_disconnect(musb);
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
musb->is_active = 0;
break;
case OTG_STATE_A_SUSPEND:
case OTG_STATE_A_WAIT_BCON:
- DBG(1, "HNP: %s timeout\n",
+ dev_dbg(musb->controller, "HNP: %s timeout\n",
otg_state_string(musb->xceiv->state));
musb_platform_set_vbus(musb, 0);
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
break;
default:
- DBG(1, "HNP: Unhandled mode %s\n",
+ dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
otg_state_string(musb->xceiv->state));
}
musb->ignore_disconnect = 0;
void __iomem *mbase = musb->mregs;
u8 reg;
- DBG(1, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
+ dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
switch (musb->xceiv->state) {
case OTG_STATE_A_PERIPHERAL:
musb_g_disconnect(musb);
- DBG(1, "HNP: back to %s\n",
+ dev_dbg(musb->controller, "HNP: back to %s\n",
otg_state_string(musb->xceiv->state));
break;
case OTG_STATE_B_HOST:
- DBG(1, "HNP: Disabling HR\n");
+ dev_dbg(musb->controller, "HNP: Disabling HR\n");
hcd->self.is_b_host = 0;
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
MUSB_DEV_MODE(musb);
/* REVISIT: Start SESSION_REQUEST here? */
break;
default:
- DBG(1, "HNP: Stopping in unknown state %s\n",
+ dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
otg_state_string(musb->xceiv->state));
}
{
irqreturn_t handled = IRQ_NONE;
- DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
+ dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
int_usb);
/* in host mode, the peripheral may issue remote wakeup.
*/
if (int_usb & MUSB_INTR_RESUME) {
handled = IRQ_HANDLED;
- DBG(3, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
+ dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
if (devctl & MUSB_DEVCTL_HM) {
#ifdef CONFIG_USB_MUSB_HDRC_HCD
if (power & MUSB_POWER_SUSPENDM) {
/* spurious */
musb->int_usb &= ~MUSB_INTR_SUSPEND;
- DBG(2, "Spurious SUSPENDM\n");
+ dev_dbg(musb->controller, "Spurious SUSPENDM\n");
break;
}
if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
&& (devctl & MUSB_DEVCTL_BDEVICE)) {
- DBG(3, "SessReq while on B state\n");
+ dev_dbg(musb->controller, "SessReq while on B state\n");
return IRQ_HANDLED;
}
- DBG(1, "SESSION_REQUEST (%s)\n",
+ dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
otg_state_string(musb->xceiv->state));
/* IRQ arrives from ID pin sense or (later, if VBUS power
break;
}
- DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
+ dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
otg_state_string(musb->xceiv->state),
devctl,
({ char *s;
#endif
if (int_usb & MUSB_INTR_SUSPEND) {
- DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
+ dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
otg_state_string(musb->xceiv->state), devctl, power);
handled = IRQ_HANDLED;
if (musb->is_active) {
#ifdef CONFIG_USB_MUSB_OTG
musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
- DBG(1, "HNP: Setting timer for b_ase0_brst\n");
+ dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
mod_timer(&musb->otg_timer, jiffies
+ msecs_to_jiffies(
OTG_TIME_B_ASE0_BRST));
break;
case OTG_STATE_B_HOST:
/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
- DBG(1, "REVISIT: SUSPEND as B_HOST\n");
+ dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
break;
default:
/* "should not happen" */
switch (musb->xceiv->state) {
case OTG_STATE_B_PERIPHERAL:
if (int_usb & MUSB_INTR_SUSPEND) {
- DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
+ dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
int_usb &= ~MUSB_INTR_SUSPEND;
goto b_host;
} else
- DBG(1, "CONNECT as b_peripheral???\n");
+ dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
break;
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: CONNECT, now b_host\n");
+ dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
b_host:
musb->xceiv->state = OTG_STATE_B_HOST;
hcd->self.is_b_host = 1;
else
usb_hcd_resume_root_hub(hcd);
- DBG(1, "CONNECT (%s) devctl %02x\n",
+ dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
otg_state_string(musb->xceiv->state), devctl);
}
#endif /* CONFIG_USB_MUSB_HDRC_HCD */
if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
- DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
+ dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
otg_state_string(musb->xceiv->state),
MUSB_MODE(musb), devctl);
handled = IRQ_HANDLED;
* stop the session.
*/
if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
- DBG(1, "BABBLE devctl: %02x\n", devctl);
+ dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
else {
ERR("Stopping host session -- babble\n");
musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
}
} else if (is_peripheral_capable()) {
- DBG(1, "BUS RESET as %s\n",
+ dev_dbg(musb->controller, "BUS RESET as %s\n",
otg_state_string(musb->xceiv->state));
switch (musb->xceiv->state) {
#ifdef CONFIG_USB_OTG
/* FALLTHROUGH */
case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
/* never use invalid T(a_wait_bcon) */
- DBG(1, "HNP: in %s, %d msec timeout\n",
+ dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
otg_state_string(musb->xceiv->state),
TA_WAIT_BCON(musb));
mod_timer(&musb->otg_timer, jiffies
musb_g_reset(musb);
break;
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: RESET (%s), to b_peripheral\n",
+ dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
otg_state_string(musb->xceiv->state));
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
musb_g_reset(musb);
musb_g_reset(musb);
break;
default:
- DBG(1, "Unhandled BUS RESET as %s\n",
+ dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
otg_state_string(musb->xceiv->state));
}
}
u8 epnum;
u16 frame;
- DBG(6, "START_OF_FRAME\n");
+ dev_dbg(musb->controller, "START_OF_FRAME\n");
handled = IRQ_HANDLED;
/* start any periodic Tx transfers waiting for current frame */
void __iomem *regs = musb->mregs;
u8 devctl = musb_readb(regs, MUSB_DEVCTL);
- DBG(2, "<== devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
/* Set INT enable registers, enable interrupts */
musb_writew(regs, MUSB_INTRTXE, musb->epmask);
/* stop IRQs, timers, ... */
musb_platform_disable(musb);
musb_generic_disable(musb);
- DBG(3, "HDRC disabled\n");
+ dev_dbg(musb->controller, "HDRC disabled\n");
/* FIXME
* - mark host and/or peripheral drivers unusable/inactive
void *mbase = musb->mregs;
int ret = 0;
- DBG(2, "<== static silicon ep config\n");
+ dev_dbg(musb->controller, "<== static silicon ep config\n");
/* FIXME pick up ep0 maxpacket size */
#endif
if (hw_ep->max_packet_sz_tx) {
- DBG(1,
+ dev_dbg(musb->controller,
"%s: hw_ep %d%s, %smax %d\n",
musb_driver_name, i,
hw_ep->is_shared_fifo ? "shared" : "tx",
hw_ep->max_packet_sz_tx);
}
if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
- DBG(1,
+ dev_dbg(musb->controller,
"%s: hw_ep %d%s, %smax %d\n",
musb_driver_name, i,
"rx",
hw_ep->max_packet_sz_rx);
}
if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
- DBG(1, "hw_ep %d not configured\n", i);
+ dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
}
return 0;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
power = musb_readb(musb->mregs, MUSB_POWER);
- DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
+ dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
musb->int_usb, musb->int_tx, musb->int_rx);
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
if (!musb->gadget_driver) {
- DBG(5, "No gadget driver loaded\n");
+ dev_dbg(musb->controller, "No gadget driver loaded\n");
return IRQ_HANDLED;
}
#endif
status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
hcd->self.uses_pio_for_control = 1;
- DBG(1, "%s mode, status %d, devctl %02x %c\n",
+ dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
"HOST", status,
musb_readb(musb->mregs, MUSB_DEVCTL),
(musb_readb(musb->mregs, MUSB_DEVCTL)
status = musb_gadget_setup(musb);
- DBG(1, "%s mode, status %d, dev%02x\n",
+ dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
status,
musb_readb(musb->mregs, MUSB_DEVCTL));
#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
"host"
#endif
- ", debug=%d\n",
- musb_driver_name, musb_debug);
+ ,
+ musb_driver_name);
return platform_driver_probe(&musb_driver, musb_probe);
}
#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
-#define DBG(level, format, args...) do { \
- if (_dbg_level(level)) \
- pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
- } while (0)
-
-extern unsigned musb_debug;
-
-static inline int _dbg_level(unsigned l)
-{
- return musb_debug >= l;
-}
-
#ifdef CONFIG_DEBUG_FS
extern int musb_init_debugfs(struct musb *musb);
extern void musb_exit_debugfs(struct musb *musb);
return;
if (request->request.dma == DMA_ADDR_INVALID) {
- DBG(20, "not unmapping a never mapped buffer\n");
+ dev_vdbg(musb->controller,
+ "not unmapping a never mapped buffer\n");
return;
}
if (request->map_state == MUSB_MAPPED) {
spin_unlock(&musb->lock);
unmap_dma_buffer(req, musb);
if (request->status == 0)
- DBG(5, "%s done request %p, %d/%d\n",
+ dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
ep->end_point.name, request,
req->request.actual, req->request.length);
else
- DBG(2, "%s request %p, %d/%d fault %d\n",
+ dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
ep->end_point.name, request,
req->request.actual, req->request.length,
request->status);
*/
static void nuke(struct musb_ep *ep, const int status)
{
+ struct musb *musb = ep->musb;
struct musb_request *req = NULL;
void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
}
value = c->channel_abort(ep->dma);
- DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
+ dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
+ ep->name, value);
c->channel_release(ep->dma);
ep->dma = NULL;
}
/* we shouldn't get here while DMA is active ... but we do ... */
if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "dma pending...\n");
+ dev_dbg(musb->controller, "dma pending...\n");
return;
}
(int)(request->length - request->actual));
if (csr & MUSB_TXCSR_TXPKTRDY) {
- DBG(5, "%s old packet still ready , txcsr %03x\n",
+ dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
musb_ep->end_point.name, csr);
return;
}
if (csr & MUSB_TXCSR_P_SENDSTALL) {
- DBG(5, "%s stalling, txcsr %03x\n",
+ dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
musb_ep->end_point.name, csr);
return;
}
- DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
+ dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
epnum, musb_ep->packet_sz, fifo_count,
csr);
}
/* host may already have the data when this message shows... */
- DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
+ dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
musb_ep->end_point.name, use_dma ? "dma" : "pio",
request->actual, request->length,
musb_readw(epio, MUSB_TXCSR),
request = &req->request;
csr = musb_readw(epio, MUSB_TXCSR);
- DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
+ dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
dma = is_dma_capable() ? musb_ep->dma : NULL;
csr |= MUSB_TXCSR_P_WZC_BITS;
csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
musb_writew(epio, MUSB_TXCSR, csr);
- DBG(20, "underrun on ep%d, req %p\n", epnum, request);
+ dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
+ epnum, request);
}
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
* SHOULD NOT HAPPEN... has with CPPI though, after
* changing SENDSTALL (and other cases); harmless?
*/
- DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
return;
}
/* Ensure writebuffer is empty. */
csr = musb_readw(epio, MUSB_TXCSR);
request->actual += musb_ep->dma->actual_len;
- DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
+ dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
epnum, csr, musb_ep->dma->actual_len, request);
}
if (csr & MUSB_TXCSR_TXPKTRDY)
return;
- DBG(4, "sending zero pkt\n");
+ dev_dbg(musb->controller, "sending zero pkt\n");
musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY);
request->zero = 0;
musb_g_giveback(musb_ep, request, 0);
req = musb_ep->desc ? next_request(musb_ep) : NULL;
if (!req) {
- DBG(4, "%s idle now\n",
+ dev_dbg(musb->controller, "%s idle now\n",
musb_ep->end_point.name);
return;
}
/* We shouldn't get here while DMA is active, but we do... */
if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "DMA pending...\n");
+ dev_dbg(musb->controller, "DMA pending...\n");
return;
}
if (csr & MUSB_RXCSR_P_SENDSTALL) {
- DBG(5, "%s stalling, RXCSR %04x\n",
+ dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
musb_ep->end_point.name, csr);
return;
}
#endif /* Mentor's DMA */
fifo_count = request->length - request->actual;
- DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
+ dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
musb_ep->end_point.name,
len, fifo_count,
musb_ep->packet_sz);
csr = musb_readw(epio, MUSB_RXCSR);
dma = is_dma_capable() ? musb_ep->dma : NULL;
- DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
+ dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
csr, dma ? " (dma)" : "", request);
if (csr & MUSB_RXCSR_P_SENTSTALL) {
csr &= ~MUSB_RXCSR_P_OVERRUN;
musb_writew(epio, MUSB_RXCSR, csr);
- DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
+ dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
if (request->status == -EINPROGRESS)
request->status = -EOVERFLOW;
}
if (csr & MUSB_RXCSR_INCOMPRX) {
/* REVISIT not necessarily an error */
- DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
}
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
/* "should not happen"; likely RXPKTRDY pending for DMA */
- DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
- "%s busy, csr %04x\n",
+ dev_dbg(musb->controller, "%s busy, csr %04x\n",
musb_ep->end_point.name, csr);
return;
}
request->actual += musb_ep->dma->actual_len;
- DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
+ dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
epnum, csr,
musb_readw(epio, MUSB_RXCSR),
musb_ep->dma->actual_len, request);
ok = musb->hb_iso_rx;
if (!ok) {
- DBG(4, "no support for high bandwidth ISO\n");
+ dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
goto fail;
}
musb_ep->hb_mult = (tmp >> 11) & 3;
goto fail;
if (tmp > hw_ep->max_packet_sz_tx) {
- DBG(4, "packet size beyond hardware FIFO size\n");
+ dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
goto fail;
}
goto fail;
if (tmp > hw_ep->max_packet_sz_rx) {
- DBG(4, "packet size beyond hardware FIFO size\n");
+ dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
goto fail;
}
spin_unlock_irqrestore(&(musb->lock), flags);
- DBG(2, "%s\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
return status;
}
struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
{
struct musb_ep *musb_ep = to_musb_ep(ep);
+ struct musb *musb = musb_ep->musb;
struct musb_request *request = NULL;
request = kzalloc(sizeof *request, gfp_flags);
if (!request) {
- DBG(4, "not enough memory\n");
+ dev_dbg(musb->controller, "not enough memory\n");
return NULL;
}
*/
void musb_ep_restart(struct musb *musb, struct musb_request *req)
{
- DBG(3, "<== %s request %p len %u on hw_ep%d\n",
+ dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
req->tx ? "TX/IN" : "RX/OUT",
&req->request, req->request.length, req->epnum);
if (request->ep != musb_ep)
return -EINVAL;
- DBG(4, "<== to %s request=%p\n", ep->name, req);
+ dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
/* request is mine now... */
request->request.actual = 0;
/* don't queue if the ep is down */
if (!musb_ep->desc) {
- DBG(4, "req %p queued to %s while ep %s\n",
+ dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
req, ep->name, "disabled");
status = -ESHUTDOWN;
goto cleanup;
break;
}
if (r != req) {
- DBG(3, "request %p not queued to %s\n", request, ep->name);
+ dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
status = -EINVAL;
goto done;
}
request = next_request(musb_ep);
if (value) {
if (request) {
- DBG(3, "request in progress, cannot halt %s\n",
+ dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
ep->name);
status = -EAGAIN;
goto done;
if (musb_ep->is_in) {
csr = musb_readw(epio, MUSB_TXCSR);
if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
- DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
+ dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
status = -EAGAIN;
goto done;
}
musb_ep->wedged = 0;
/* set/clear the stall and toggle bits */
- DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
+ dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
if (musb_ep->is_in) {
csr = musb_readw(epio, MUSB_TXCSR);
csr |= MUSB_TXCSR_P_WZC_BITS
/* maybe start the first request in the queue */
if (!musb_ep->busy && !value && request) {
- DBG(3, "restarting the request\n");
+ dev_dbg(musb->controller, "restarting the request\n");
musb_ep_restart(musb, request);
}
case OTG_STATE_B_IDLE:
/* Start SRP ... OTG not required. */
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(2, "Sending SRP: devctl: %02x\n", devctl);
+ dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(mregs, MUSB_DEVCTL, devctl);
devctl = musb_readb(mregs, MUSB_DEVCTL);
status = 0;
goto done;
default:
- DBG(2, "Unhandled wake: %s\n",
+ dev_dbg(musb->controller, "Unhandled wake: %s\n",
otg_state_string(musb->xceiv->state));
goto done;
}
power = musb_readb(mregs, MUSB_POWER);
power |= MUSB_POWER_RESUME;
musb_writeb(mregs, MUSB_POWER, power);
- DBG(2, "issue wakeup\n");
+ dev_dbg(musb->controller, "issue wakeup\n");
/* FIXME do this next chunk in a timer callback, no udelay */
mdelay(2);
/* FIXME if on, HdrcStart; if off, HdrcStop */
- DBG(3, "gadget %s D+ pullup %s\n",
+ dev_dbg(musb->controller, "gadget %s D+ pullup %s\n",
musb->gadget_driver->function, is_on ? "on" : "off");
musb_writeb(musb->mregs, MUSB_POWER, power);
}
#if 0
static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
{
- DBG(2, "<= %s =>\n", __func__);
+ dev_dbg(musb->controller, "<= %s =>\n", __func__);
/*
* FIXME iff driver's softconnect flag is set (as it is during probe,
/* driver must be initialized to support peripheral mode */
if (!musb) {
- DBG(1, "no dev??\n");
+ dev_dbg(musb->controller, "no dev??\n");
retval = -ENODEV;
goto err0;
}
pm_runtime_get_sync(musb->controller);
- DBG(3, "registering driver %s\n", driver->function);
+ dev_dbg(musb->controller, "registering driver %s\n", driver->function);
if (musb->gadget_driver) {
- DBG(1, "%s is already bound to %s\n",
+ dev_dbg(musb->controller, "%s is already bound to %s\n",
musb_driver_name,
musb->gadget_driver->driver.name);
retval = -EBUSY;
retval = bind(&musb->g);
if (retval) {
- DBG(3, "bind to driver %s failed --> %d\n",
+ dev_dbg(musb->controller, "bind to driver %s failed --> %d\n",
driver->driver.name, retval);
goto err1;
}
if (is_otg_enabled(musb)) {
struct usb_hcd *hcd = musb_to_hcd(musb);
- DBG(3, "OTG startup...\n");
+ dev_dbg(musb->controller, "OTG startup...\n");
/* REVISIT: funcall to other code, which also
* handles power budgeting ... this way also
*/
retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
if (retval < 0) {
- DBG(1, "add_hcd failed, %d\n", retval);
+ dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
goto err2;
}
stop_activity(musb, driver);
otg_set_peripheral(musb->xceiv, NULL);
- DBG(3, "unregistering driver %s\n", driver->function);
+ dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
spin_unlock_irqrestore(&musb->lock, flags);
driver->unbind(&musb->g);
u8 devctl;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- DBG(3, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
switch (musb->xceiv->state) {
case OTG_STATE_B_IDLE:
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(3, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
/* clear HR */
musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
switch (musb->xceiv->state) {
default:
#ifdef CONFIG_USB_MUSB_OTG
- DBG(2, "Unhandled disconnect %s, setting a_idle\n",
+ dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
otg_state_string(musb->xceiv->state));
musb->xceiv->state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
u8 power;
- DBG(3, "<== %s addr=%x driver '%s'\n",
+ dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
(devctl & MUSB_DEVCTL_BDEVICE)
? "B-Device" : "A-Device",
musb_readb(mbase, MUSB_FADDR),
void __iomem *mbase = musb->mregs;
u8 devctl;
- DBG(1, "HNP: Setting HR\n");
+ dev_dbg(musb->controller, "HNP: Setting HR\n");
devctl = musb_readb(mbase, MUSB_DEVCTL);
musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
}
/* Maybe start the first request in the queue */
request = next_request(musb_ep);
if (!musb_ep->busy && request) {
- DBG(3, "restarting the request\n");
+ dev_dbg(musb->controller, "restarting the request\n");
musb_ep_restart(musb, request);
}
if (!req) {
/* WARN_ON(1); */
- DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
+ dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
return;
}
/* NOTE: earlier 2.6 versions changed setup packets to host
* order, but now USB packets always stay in USB byte order.
*/
- DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
+ dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
req->bRequestType,
req->bRequest,
le16_to_cpu(req->wValue),
csr = musb_readw(regs, MUSB_CSR0);
len = musb_readb(regs, MUSB_COUNT0);
- DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
+ dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
csr, len,
musb_readb(mbase, MUSB_FADDR),
decode_ep0stage(musb->ep0_state));
/* enter test mode if needed (exit by reset) */
else if (musb->test_mode) {
- DBG(1, "entering TESTMODE\n");
+ dev_dbg(musb->controller, "entering TESTMODE\n");
if (MUSB_TEST_PACKET == musb->test_mode_nr)
musb_load_testpacket(musb);
break;
}
- DBG(3, "handled %d, csr %04x, ep0stage %s\n",
+ dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
handled, csr,
decode_ep0stage(musb->ep0_state));
if (handled < 0) {
musb_ep_select(mbase, 0);
stall:
- DBG(3, "stall (%d)\n", handled);
+ dev_dbg(musb->controller, "stall (%d)\n", handled);
musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
finish:
status = 0;
break;
default:
- DBG(1, "ep0 request queued in state %d\n",
+ dev_dbg(musb->controller, "ep0 request queued in state %d\n",
musb->ep0_state);
status = -EINVAL;
goto cleanup;
/* add request to the list */
list_add_tail(&req->list, &ep->req_list);
- DBG(3, "queue to %s (%s), length=%d\n",
+ dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
req->request.length);
musb->ackpend = 0;
break;
default:
- DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
+ dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
status = -EINVAL;
}
*/
static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
{
+ struct musb *musb = ep->musb;
void __iomem *epio = ep->regs;
u16 csr;
u16 lastcsr = 0;
csr = musb_readw(epio, MUSB_TXCSR);
while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
if (csr != lastcsr)
- DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+ dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
lastcsr = csr;
csr |= MUSB_TXCSR_FLUSHFIFO;
musb_writew(epio, MUSB_TXCSR, csr);
len = urb->transfer_buffer_length - urb->actual_length;
}
- DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
+ dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
qh, urb, address, qh->epnum,
is_in ? "in" : "out",
({char *s; switch (qh->type) {
switch (qh->type) {
case USB_ENDPOINT_XFER_ISOC:
case USB_ENDPOINT_XFER_INT:
- DBG(3, "check whether there's still time for periodic Tx\n");
+ dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
frame = musb_readw(mbase, MUSB_FRAME);
/* FIXME this doesn't implement that scheduling policy ...
* or handle framecounter wrapping
} else {
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
- DBG(1, "SOF for %d\n", epnum);
+ dev_dbg(musb->controller, "SOF for %d\n", epnum);
#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
#endif
break;
default:
start:
- DBG(4, "Start TX%d %s\n", epnum,
+ dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
hw_ep->tx_channel ? "dma" : "pio");
if (!hw_ep->tx_channel)
__releases(musb->lock)
__acquires(musb->lock)
{
- DBG(({ int level; switch (status) {
- case 0:
- level = 4;
- break;
- /* common/boring faults */
- case -EREMOTEIO:
- case -ESHUTDOWN:
- case -ECONNRESET:
- case -EPIPE:
- level = 3;
- break;
- default:
- level = 2;
- break;
- }; level; }),
+ dev_dbg(musb->controller,
"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
urb, urb->complete, status,
usb_pipedevice(urb->pipe),
}
if (qh != NULL && qh->is_ready) {
- DBG(4, "... next ep%d %cX urb %p\n",
+ dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
musb_start_urb(musb, is_in, qh);
}
/* musb_ep_select(mbase, epnum); */
rx_count = musb_readw(epio, MUSB_RXCOUNT);
- DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+ dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
urb->transfer_buffer, qh->offset,
urb->transfer_buffer_length);
status = -EOVERFLOW;
urb->error_count++;
}
- DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
length = rx_count;
if (rx_count > length) {
if (urb->status == -EINPROGRESS)
urb->status = -EOVERFLOW;
- DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
length = rx_count;
struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
u16 packet_sz = qh->maxpacket;
- DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
+ dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
"h_addr%02x h_port%02x bytes %d\n",
is_out ? "-->" : "<--",
epnum, urb, urb->dev->speed,
}
csr |= MUSB_RXCSR_H_REQPKT;
- DBG(7, "RXCSR%d := %04x\n", epnum, csr);
+ dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
}
request = (struct usb_ctrlrequest *) urb->setup_packet;
if (!request->wLength) {
- DBG(4, "start no-DATA\n");
+ dev_dbg(musb->controller, "start no-DATA\n");
break;
} else if (request->bRequestType & USB_DIR_IN) {
- DBG(4, "start IN-DATA\n");
+ dev_dbg(musb->controller, "start IN-DATA\n");
musb->ep0_stage = MUSB_EP0_IN;
more = true;
break;
} else {
- DBG(4, "start OUT-DATA\n");
+ dev_dbg(musb->controller, "start OUT-DATA\n");
musb->ep0_stage = MUSB_EP0_OUT;
more = true;
}
if (fifo_count) {
fifo_dest = (u8 *) (urb->transfer_buffer
+ urb->actual_length);
- DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
+ dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
fifo_count,
(fifo_count == 1) ? "" : "s",
fifo_dest);
? musb_readb(epio, MUSB_COUNT0)
: 0;
- DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
+ dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
csr, qh, len, urb, musb->ep0_stage);
/* if we just did status stage, we are done */
/* prepare status */
if (csr & MUSB_CSR0_H_RXSTALL) {
- DBG(6, "STALLING ENDPOINT\n");
+ dev_dbg(musb->controller, "STALLING ENDPOINT\n");
status = -EPIPE;
} else if (csr & MUSB_CSR0_H_ERROR) {
- DBG(2, "no response, csr0 %04x\n", csr);
+ dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
status = -EPROTO;
} else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
- DBG(2, "control NAK timeout\n");
+ dev_dbg(musb->controller, "control NAK timeout\n");
/* NOTE: this code path would be a good place to PAUSE a
* control transfer, if another one is queued, so that
}
if (status) {
- DBG(6, "aborting\n");
+ dev_dbg(musb->controller, "aborting\n");
retval = IRQ_HANDLED;
if (urb)
urb->status = status;
/* flag status stage */
musb->ep0_stage = MUSB_EP0_STATUS;
- DBG(5, "ep0 STATUS, csr %04x\n", csr);
+ dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
}
musb_writew(epio, MUSB_CSR0, csr);
/* with CPPI, DMA sometimes triggers "extra" irqs */
if (!urb) {
- DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
pipe = urb->pipe;
dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
- DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
+ dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
dma ? ", dma" : "");
/* check for errors */
if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
/* dma was disabled, fifo flushed */
- DBG(3, "TX end %d stall\n", epnum);
+ dev_dbg(musb->controller, "TX end %d stall\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (tx_csr & MUSB_TXCSR_H_ERROR) {
/* (NON-ISO) dma was disabled, fifo flushed */
- DBG(3, "TX 3strikes on ep=%d\n", epnum);
+ dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
status = -ETIMEDOUT;
} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
- DBG(6, "TX end=%d device not responding\n", epnum);
+ dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
/* NOTE: this code path would be a good place to PAUSE a
* transfer, if there's some other (nonperiodic) tx urb
/* second cppi case */
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
* FIFO mode too...
*/
if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
- DBG(2, "DMA complete but packet still in FIFO, "
+ dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
"CSR %04x\n", tx_csr);
return;
}
return;
}
} else if (tx_csr & MUSB_TXCSR_DMAENAB) {
- DBG(1, "not complete, but DMA enabled?\n");
+ dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
return;
}
* usbtest #11 (unlinks) triggers it regularly, sometimes
* with fifo full. (Only with DMA??)
*/
- DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
+ dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
musb_readw(epio, MUSB_RXCOUNT));
musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
return;
pipe = urb->pipe;
- DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
+ dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
epnum, rx_csr, urb->actual_length,
dma ? dma->actual_len : 0);
/* check for errors, concurrent stall & unlink is not really
* handled yet! */
if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
- DBG(3, "RX end %d STALL\n", epnum);
+ dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (rx_csr & MUSB_RXCSR_H_ERROR) {
- DBG(3, "end %d RX proto error\n", epnum);
+ dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
status = -EPROTO;
musb_writeb(epio, MUSB_RXINTERVAL, 0);
} else if (rx_csr & MUSB_RXCSR_DATAERROR) {
if (USB_ENDPOINT_XFER_ISOC != qh->type) {
- DBG(6, "RX end %d NAK timeout\n", epnum);
+ dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
/* NOTE: NAKing is *NOT* an error, so we want to
* continue. Except ... if there's a request for
goto finish;
} else {
- DBG(4, "RX end %d ISO data error\n", epnum);
+ dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
/* packet error reported later */
iso_err = true;
}
} else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
- DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
+ dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
epnum);
status = -EPROTO;
}
done = true;
}
- DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
+ dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
xfer_len, dma ? ", dma" : "");
rx_csr &= ~MUSB_RXCSR_H_REQPKT;
MUSB_RXCSR_H_WZC_BITS | val);
}
- DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
+ dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
done ? "off" : "reset",
musb_readw(epio, MUSB_RXCSR),
musb_readw(epio, MUSB_RXCOUNT));
rx_count = musb_readw(epio, MUSB_RXCOUNT);
- DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
+ dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
epnum, rx_count,
urb->transfer_dma
+ urb->actual_length,
d_status = -EOVERFLOW;
urb->error_count++;
}
- DBG(2, "** OVERFLOW %d into %d\n",\
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
rx_count, d->length);
length = d->length;
usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
done = musb_host_packet_rx(musb, urb,
epnum, iso_err);
- DBG(6, "read %spacket\n", done ? "last " : "");
+ dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
}
}
idle = 1;
qh->mux = 0;
hw_ep = musb->endpoints + best_end;
- DBG(4, "qh %p periodic slot %d\n", qh, best_end);
+ dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
success:
if (head) {
idle = list_empty(head);
static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
{
struct musb_hw_ep *ep = qh->hw_ep;
+ struct musb *musb = ep->musb;
void __iomem *epio = ep->regs;
unsigned hw_end = ep->epnum;
void __iomem *regs = ep->musb->mregs;
dma = is_in ? ep->rx_channel : ep->tx_channel;
if (dma) {
status = ep->musb->dma_controller->channel_abort(dma);
- DBG(status ? 1 : 3,
+ dev_dbg(musb->controller,
"abort %cX%d DMA for urb %p --> %d\n",
is_in ? 'R' : 'T', ep->epnum,
urb, status);
int is_in = usb_pipein(urb->pipe);
int ret;
- DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
+ dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
usb_pipedevice(urb->pipe),
usb_pipeendpoint(urb->pipe),
is_in ? "in" : "out");
break;
}
- DBG(3, "Root port suspended, power %02x\n", power);
+ dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
musb->port1_status |= USB_PORT_STAT_SUSPEND;
switch (musb->xceiv->state) {
break;
#endif
default:
- DBG(1, "bogus rh suspend? %s\n",
+ dev_dbg(musb->controller, "bogus rh suspend? %s\n",
otg_state_string(musb->xceiv->state));
}
} else if (power & MUSB_POWER_SUSPENDM) {
power |= MUSB_POWER_RESUME;
musb_writeb(mbase, MUSB_POWER, power);
- DBG(3, "Root port resuming, power %02x\n", power);
+ dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
/* later, GetPortStatus will stop RESUME signaling */
musb->port1_status |= MUSB_PORT_STAT_RESUME;
#ifdef CONFIG_USB_MUSB_OTG
if (musb->xceiv->state == OTG_STATE_B_IDLE) {
- DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
+ dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
musb->port1_status &= ~USB_PORT_STAT_RESET;
return;
}
musb->port1_status &= ~USB_PORT_STAT_ENABLE;
musb->rh_timer = jiffies + msecs_to_jiffies(50);
} else {
- DBG(4, "root port reset stopped\n");
+ dev_dbg(musb->controller, "root port reset stopped\n");
musb_writeb(mbase, MUSB_POWER,
power & ~MUSB_POWER_RESET);
power = musb_readb(mbase, MUSB_POWER);
if (power & MUSB_POWER_HSMODE) {
- DBG(4, "high-speed device connected\n");
+ dev_dbg(musb->controller, "high-speed device connected\n");
musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
}
musb->xceiv->state = OTG_STATE_B_IDLE;
break;
default:
- DBG(1, "host disconnect (%s)\n",
+ dev_dbg(musb->controller, "host disconnect (%s)\n",
otg_state_string(musb->xceiv->state));
}
}
default:
goto error;
}
- DBG(5, "clear feature %d\n", wValue);
+ dev_dbg(musb->controller, "clear feature %d\n", wValue);
musb->port1_status &= ~(1 << wValue);
break;
case GetHubDescriptor:
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
- DBG(4, "root port resume stopped, power %02x\n",
+ dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
power);
musb_writeb(musb->mregs, MUSB_POWER, power);
(__le32 *) buf);
/* port change status is more interesting */
- DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n",
+ dev_dbg(musb->controller, "port status %08x\n",
musb->port1_status);
break;
case SetPortFeature:
default:
goto error;
}
- DBG(5, "set feature %d\n", wValue);
+ dev_dbg(musb->controller, "set feature %d\n", wValue);
musb->port1_status |= 1 << wValue;
break;
{
struct musb_dma_channel *musb_channel = channel->private_data;
struct musb_dma_controller *controller = musb_channel->controller;
+ struct musb *musb = controller->private_data;
void __iomem *mbase = controller->base;
u8 bchannel = musb_channel->idx;
u16 csr = 0;
- DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
+ dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
channel, packet_sz, dma_addr, len, mode);
if (mode) {
struct musb_dma_controller *controller = musb_channel->controller;
struct musb *musb = controller->private_data;
- DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
+ dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
musb_channel->epnum,
musb_channel->transmit ? "Tx" : "Rx",
packet_sz, dma_addr, len, mode);
#endif
if (!int_hsdma) {
- DBG(2, "spurious DMA irq\n");
+ dev_dbg(musb->controller, "spurious DMA irq\n");
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
musb_channel = (struct musb_dma_channel *)
}
}
- DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
+ dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
if (!int_hsdma)
goto done;
channel->actual_len = addr
- musb_channel->start_addr;
- DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
+ dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
channel, musb_channel->start_addr,
addr, channel->actual_len,
musb_channel->len,
if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
- DBG(1, "root port resume stopped, power %02x\n", power);
+ dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
musb_writeb(musb->mregs, MUSB_POWER, power);
musb->is_active = 1;
musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
- DBG(4, "%s active, deleting timer\n",
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
- DBG(4, "Longer idle timer already pending, ignoring\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
- DBG(4, "%s inactive, for idle timer for %lu ms\n",
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- DBG(1, "VBUS %s, devctl %02x "
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
switch (event) {
case USB_EVENT_ID:
- DBG(4, "ID GND\n");
+ dev_dbg(musb->controller, "ID GND\n");
if (is_otg_enabled(musb)) {
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
break;
case USB_EVENT_VBUS:
- DBG(4, "VBUS Connect\n");
+ dev_dbg(musb->controller, "VBUS Connect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (musb->gadget_driver)
break;
case USB_EVENT_NONE:
- DBG(4, "VBUS Disconnect\n");
+ dev_dbg(musb->controller, "VBUS Disconnect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
otg_shutdown(musb->xceiv);
break;
default:
- DBG(4, "ID float\n");
+ dev_dbg(musb->controller, "ID float\n");
return NOTIFY_DONE;
}
status = otg_register_notifier(musb->xceiv, &musb->nb);
if (status)
- DBG(1, "notification register failed\n");
+ dev_dbg(musb->controller, "notification register failed\n");
setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
- DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
+ dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
- DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
+ dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
phy_otg_ctrl = 0;
prefetch(buf);
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'T', epnum, fifo, len, buf);
if (epnum)
void __iomem *fifo = hw_ep->fifo;
u8 epnum = hw_ep->epnum;
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', epnum, fifo, len, buf);
if (epnum)
}
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
- DBG(2, "draw max %d mA VBUS\n", mA);
+ dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
return 0;
}
reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
- DBG(6, "idle, wake on %02x\n", wakeup_enables);
+ dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
}
/*
if ((musb->a_wait_bcon != 0)
&& (musb->idle_timeout == 0
|| time_after(jiffies, musb->idle_timeout))) {
- DBG(4, "Nothing connected %s, turning off VBUS\n",
+ dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
otg_state_string(musb->xceiv->state));
}
/* FALLTHROUGH */
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
- DBG(4, "%s active, deleting timer\n",
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
- DBG(4, "Longer idle timer already pending, ignoring\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
- DBG(4, "%s inactive, for idle timer for %lu ms\n",
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
musb_writel(tbase, TUSB_DEV_CONF, conf);
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL),
musb_readl(tbase, TUSB_DEV_OTG_STAT),
#endif
default:
- DBG(2, "Trying to set mode %i\n", musb_mode);
+ dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
return -EINVAL;
}
default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
else
default_a = is_host_enabled(musb);
- DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
+ dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
musb->xceiv->default_a = default_a;
tusb_musb_set_vbus(musb, default_a);
#endif
if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
- DBG(1, "Forcing disconnect (no interrupt)\n");
+ dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
if (musb->xceiv->state != OTG_STATE_B_IDLE) {
/* INTR_DISCONNECT can hide... */
musb->xceiv->state = OTG_STATE_B_IDLE;
}
musb->is_active = 0;
}
- DBG(2, "vbus change, %s, otg %03x\n",
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
idle_timeout = jiffies + (1 * HZ);
schedule_work(&musb->irq_work);
} else /* A-dev state machine */ {
- DBG(2, "vbus change, %s, otg %03x\n",
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
case OTG_STATE_A_IDLE:
- DBG(2, "Got SRP, turning on VBUS\n");
+ dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
musb_platform_set_vbus(musb, 1);
/* CONNECT can wake if a_wait_bcon is set */
if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
u8 devctl;
- DBG(4, "%s timer, %03x\n",
+ dev_dbg(musb->controller, "%s timer, %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
if ((devctl & MUSB_DEVCTL_VBUS)
!= MUSB_DEVCTL_VBUS) {
- DBG(2, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
break;
}
musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
- DBG(3, "TUSB IRQ %08x\n", int_src);
+ dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
musb->int_usb = (u8) int_src;
reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
if (reg == i)
break;
- DBG(6, "TUSB NOR not ready\n");
+ dev_dbg(musb->controller, "TUSB NOR not ready\n");
}
/* work around issue 13 (2nd half) */
musb->is_active = 1;
schedule_work(&musb->irq_work);
}
- DBG(3, "wake %sactive %02x\n",
+ dev_dbg(musb->controller, "wake %sactive %02x\n",
musb->is_active ? "" : "in", reg);
/* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
- DBG(3, "DMA IRQ %08x\n", dma_src);
+ dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
real_dma_src = ~real_dma_src & dma_src;
if (tusb_dma_omap() && real_dma_src) {
int tx_source = (real_dma_src & 0xffff);
for (i = 1; i <= 15; i++) {
if (tx_source & (1 << i)) {
- DBG(3, "completing ep%i %s\n", i, "tx");
+ dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
musb_dma_completion(musb, i, 1);
}
}
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
+ /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
+ /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
if (reg != 0) {
- DBG(3, "ep%i dmareq0 is busy for ep%i\n",
+ dev_dbg(musb->controller, "ep%i dmareq0 is busy for ep%i\n",
chdat->epnum, reg & 0xf);
return -EAGAIN;
}
if (ch_status != OMAP_DMA_BLOCK_IRQ)
printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
- DBG(3, "ep%i %s dma callback ch: %i status: %x\n",
+ dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, ch_status);
/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
if (unlikely(remaining > chdat->transfer_len)) {
- DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
+ dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
chdat->tx ? "tx" : "rx", chdat->ch,
remaining);
remaining = 0;
channel->actual_len = chdat->transfer_len - remaining;
pio = chdat->len - channel->actual_len;
- DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
+ dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
/* Transfer remaining 1 - 31 bytes */
if (pio > 0 && pio < 32) {
u8 *buf;
- DBG(3, "Using PIO for remaining %lu bytes\n", pio);
+ dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
if (chdat->tx) {
dma_unmap_single(dev, chdat->dma_addr,
u16 csr;
if (chdat->tx) {
- DBG(3, "terminating short tx packet\n");
+ dev_dbg(musb->controller, "terminating short tx packet\n");
musb_ep_select(mbase, chdat->epnum);
csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
if (dma_remaining) {
- DBG(2, "Busy %s dma ch%i, not using: %08x\n",
+ dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
chdat->tx ? "tx" : "rx", chdat->ch,
dma_remaining);
return false;
sync_dev = chdat->sync_dev;
} else {
if (tusb_omap_use_shared_dmareq(chdat) != 0) {
- DBG(3, "could not get dma for ep%i\n", chdat->epnum);
+ dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
return false;
}
if (tusb_dma->ch < 0) {
dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
- DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
+ dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, dma_addr, chdat->transfer_len, len,
chdat->transfer_packet_sz, packet_sz);
dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
}
- DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
+ dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
((dma_addr & 0x3) == 0) ? "sync" : "async",
/* REVISIT: Why does dmareq5 not work? */
if (hw_ep->epnum == 0) {
- DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
+ dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
return NULL;
}
chdat->ch = -1;
}
- DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
+ dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
chdat->epnum,
chdat->tx ? "tx" : "rx",
chdat->ch >= 0 ? "dedicated" : "shared",
free_dmareq:
tusb_omap_dma_free_dmareq(chdat);
- DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
+ dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
channel->status = MUSB_DMA_STATUS_UNKNOWN;
return NULL;
void __iomem *tbase = musb->ctrl_base;
u32 reg;
- DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
+ dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
if (chdat->tx)
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