drm/i915/icp: add ICP gmbus and gpio support

In ICP, there are three TC ports and 3 DDI ports.

v2:
 - Correct Pin mapping.
v3:
 - Update pin mapping into per platform implementation
   rather than previous approach of port wise mapping.
v4:
 - Update GMBUS_NUM_PINS (Paulo)
v5:
 - rebase.
v6:
 - Update function name, GMBUS_PIN_NUM (Paulo)
v7 (from Paulo):
 - Make it apply.
v8 (from Paulo):
 - Maintain consistent if ladder ordering.

Suggested by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180111180010.24357-8-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79fa4739b64bc9e1dd74c8aaf4ae7a70856b4d81..1b28669f4f997b6a20288c429897eddcf6660c21 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3063,7 +3063,12 @@ enum i915_power_well_id {
 #define   GMBUS_PIN_2_BXT      2
 #define   GMBUS_PIN_3_BXT      3
 #define   GMBUS_PIN_4_CNP      4
-#define   GMBUS_NUM_PINS       7 /* including 0 */
+#define   GMBUS_PIN_9_TC1_ICP  9
+#define   GMBUS_PIN_10_TC2_ICP 10
+#define   GMBUS_PIN_11_TC3_ICP 11
+#define   GMBUS_PIN_12_TC4_ICP 12
+
+#define   GMBUS_NUM_PINS       13 /* including 0 */
 #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT     (1<<31)
 #define   GMBUS_SW_RDY         (1<<30)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 93e97f9e1aacdf886674995a0198ae9e0ebe2728..303c6d5acbded9d82c04904b446d6da9d416678b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1943,6 +1943,37 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
        return ddc_pin;
 }
 
+static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+       u8 ddc_pin;
+
+       switch (port) {
+       case PORT_A:
+               ddc_pin = GMBUS_PIN_1_BXT;
+               break;
+       case PORT_B:
+               ddc_pin = GMBUS_PIN_2_BXT;
+               break;
+       case PORT_C:
+               ddc_pin = GMBUS_PIN_9_TC1_ICP;
+               break;
+       case PORT_D:
+               ddc_pin = GMBUS_PIN_10_TC2_ICP;
+               break;
+       case PORT_E:
+               ddc_pin = GMBUS_PIN_11_TC3_ICP;
+               break;
+       case PORT_F:
+               ddc_pin = GMBUS_PIN_12_TC4_ICP;
+               break;
+       default:
+               MISSING_CASE(port);
+               ddc_pin = GMBUS_PIN_2_BXT;
+               break;
+       }
+       return ddc_pin;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
                              enum port port)
 {
@@ -1985,6 +2016,8 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
                ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
        else if (HAS_PCH_CNP(dev_priv))
                ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
+       else if (IS_ICELAKE(dev_priv))
+               ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
        else
                ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
 

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index ef9f91a0b0c9869caf1736e2d5fbaf77ab589560..ad1b1a345f2e1cae7ce513bf174747ed1a50f962 100644 (file)
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -75,11 +75,22 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
        [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_icp[] = {
+       [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
+       [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
+       [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
+       [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
+       [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
+       [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
                                             unsigned int pin)
 {
-       if (HAS_PCH_CNP(dev_priv))
+       if (HAS_PCH_ICP(dev_priv))
+               return &gmbus_pins_icp[pin];
+       else if (HAS_PCH_CNP(dev_priv))
                return &gmbus_pins_cnp[pin];
        else if (IS_GEN9_LP(dev_priv))
                return &gmbus_pins_bxt[pin];
@@ -96,7 +107,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
        unsigned int size;
 
-       if (HAS_PCH_CNP(dev_priv))
+       if (HAS_PCH_ICP(dev_priv))
+               size = ARRAY_SIZE(gmbus_pins_icp);
+       else if (HAS_PCH_CNP(dev_priv))
                size = ARRAY_SIZE(gmbus_pins_cnp);
        else if (IS_GEN9_LP(dev_priv))
                size = ARRAY_SIZE(gmbus_pins_bxt);