qed: Add driver support for 20G link speed.
authorSudarsana Reddy Kalluru <sudarsana.kalluru@cavium.com>
Tue, 2 Oct 2018 13:16:11 +0000 (06:16 -0700)
committerDavid S. Miller <davem@davemloft.net>
Tue, 2 Oct 2018 18:29:40 +0000 (11:29 -0700)
Add driver support for configuring/reading the 20G link speed.

Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed_dev.c
drivers/net/ethernet/qlogic/qed/qed_hsi.h
drivers/net/ethernet/qlogic/qed/qed_main.c
include/linux/qed/qed_if.h

index 0fbeafeef7a04afd6534e634359c279432d47eee..7ceb2b97538d25d767c3d8cc7e7ab79d8b03e760 100644 (file)
@@ -2679,6 +2679,9 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
        case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
                link->speed.forced_speed = 10000;
                break;
+       case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
+               link->speed.forced_speed = 20000;
+               break;
        case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
                link->speed.forced_speed = 25000;
                break;
index d4d08383c75334c8991993871012c4e66debbe47..56578f888b705bf4e9c03c6fdb9bf73cf5ec921c 100644 (file)
@@ -13154,6 +13154,7 @@ struct nvm_cfg1_port {
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET         0
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G             0x1
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G            0x2
+#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G             0x4
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G            0x8
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G            0x10
 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G            0x20
@@ -13164,6 +13165,7 @@ struct nvm_cfg1_port {
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                   0x0
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                                0x1
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                       0x2
+#define NVM_CFG1_PORT_DRV_LINK_SPEED_20G                        0x3
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                       0x4
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                       0x5
 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                       0x6
index 2094d86a7a087dac2eed0fe77bd71f66e7d975c7..75d217aaf8cec142dbe572eb6f5abc101acabf31 100644 (file)
@@ -1337,6 +1337,9 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
                if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
                        link_params->speed.advertised_speeds |=
                            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
+               if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT)
+                       link_params->speed.advertised_speeds |=
+                               NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
                if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
                        link_params->speed.advertised_speeds |=
                            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
@@ -1502,6 +1505,9 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
        if (params.speed.advertised_speeds &
            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
                if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
+       if (params.speed.advertised_speeds &
+           NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
+               if_link->advertised_caps |= QED_LM_20000baseKR2_Full_BIT;
        if (params.speed.advertised_speeds &
            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
                if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
@@ -1522,6 +1528,9 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
        if (link_caps.speed_capabilities &
            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
                if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
+       if (link_caps.speed_capabilities &
+           NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
+               if_link->supported_caps |= QED_LM_20000baseKR2_Full_BIT;
        if (link_caps.speed_capabilities &
            NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
                if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
@@ -1559,6 +1568,8 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
                if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
        if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
                if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
+       if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G)
+               if_link->lp_caps |= QED_LM_20000baseKR2_Full_BIT;
        if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
                if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
        if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
index 8cd34645e892623b71d5ee446dfb6a4423594e93..dee3c9c744f7526bbcb8ffa061ab22e17a9c13a4 100644 (file)
@@ -670,10 +670,11 @@ enum qed_link_mode_bits {
        QED_LM_1000baseT_Half_BIT = BIT(4),
        QED_LM_1000baseT_Full_BIT = BIT(5),
        QED_LM_10000baseKR_Full_BIT = BIT(6),
-       QED_LM_25000baseKR_Full_BIT = BIT(7),
-       QED_LM_40000baseLR4_Full_BIT = BIT(8),
-       QED_LM_50000baseKR2_Full_BIT = BIT(9),
-       QED_LM_100000baseKR4_Full_BIT = BIT(10),
+       QED_LM_20000baseKR2_Full_BIT = BIT(7),
+       QED_LM_25000baseKR_Full_BIT = BIT(8),
+       QED_LM_40000baseLR4_Full_BIT = BIT(9),
+       QED_LM_50000baseKR2_Full_BIT = BIT(10),
+       QED_LM_100000baseKR4_Full_BIT = BIT(11),
        QED_LM_COUNT = 11
 };