mlxsw: spectrum: Add support for 400Gbps (50Gbps per lane) link modes

Extend speed support with 400Gbps

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 7b538e698a3dde4bc24fb3088d76b9458e8c5d26..f5e39758c6ac82eed70612b265ceebf140271495 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -4111,6 +4111,7 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4           BIT(9)
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2                BIT(10)
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4                BIT(12)
+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8                         BIT(15)
 
 /* reg_ptys_ext_eth_proto_cap
  * Extended Ethernet port supported speeds and protocols.

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
index 3c5154e559b2122595b3a6d9c3dd05d58622d269..ae3c4da11520ba236580ce17ef707c8c5248959f 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
@@ -2912,9 +2912,22 @@ mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
        ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
 
+static const enum ethtool_link_mode_bit_indices
+mlxsw_sp2_mask_ethtool_400gaui_8[] = {
+       ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
+       ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
+       ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
+       ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
+       ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
+};
+
+#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
+       ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
+
 #define MLXSW_SP_PORT_MASK_WIDTH_1X    BIT(0)
 #define MLXSW_SP_PORT_MASK_WIDTH_2X    BIT(1)
 #define MLXSW_SP_PORT_MASK_WIDTH_4X    BIT(2)
+#define MLXSW_SP_PORT_MASK_WIDTH_8X    BIT(3)
 
 static u8 mlxsw_sp_port_mask_width_get(u8 width)
 {
@@ -2925,6 +2938,8 @@ static u8 mlxsw_sp_port_mask_width_get(u8 width)
                return MLXSW_SP_PORT_MASK_WIDTH_2X;
        case 4:
                return MLXSW_SP_PORT_MASK_WIDTH_4X;
+       case 8:
+               return MLXSW_SP_PORT_MASK_WIDTH_8X;
        default:
                WARN_ON_ONCE(1);
                return 0;
@@ -2946,7 +2961,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_100,
        },
        {
@@ -2955,7 +2971,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_1000,
        },
        {
@@ -2964,7 +2981,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_2500,
        },
        {
@@ -2973,7 +2991,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_5000,
        },
        {
@@ -2982,14 +3001,16 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_10000,
        },
        {
                .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
                .mask_ethtool   = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
-               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
+               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_40000,
        },
        {
@@ -2998,7 +3019,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
                                  MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_25000,
        },
        {
@@ -3006,7 +3028,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
                .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_2X |
-                                 MLXSW_SP_PORT_MASK_WIDTH_4X,
+                                 MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_50000,
        },
        {
@@ -3020,7 +3043,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
                .mask_ethtool   = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
-               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
+               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_100000,
        },
        {
@@ -3034,9 +3058,17 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
                .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
                .mask_ethtool   = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
                .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
-               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
+               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
+                                 MLXSW_SP_PORT_MASK_WIDTH_8X,
                .speed          = SPEED_200000,
        },
+       {
+               .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
+               .mask_ethtool   = mlxsw_sp2_mask_ethtool_400gaui_8,
+               .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
+               .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_8X,
+               .speed          = SPEED_400000,
+       },
 };
 
 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)