drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL

Replace the magic bit with the proper symbolic name for instructing
MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT
address (still virtual!) on gen4+.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706142323.25699-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 1193dd36913a6b8adfbcabfa6047604886f2129e..ab662dabcff7a6fdfba578e6710c468faad334d5 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
                        *cmd++ = val;
                } else if (gen >= 4) {
                        *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
-                               (gen < 6 ? 1 << 22 : 0);
+                               (gen < 6 ? MI_USE_GGTT : 0);
                        *cmd++ = 0;
                        *cmd++ = offset;
                        *cmd++ = val;
                } else {
-                       *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+                       *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
                        *cmd++ = offset;
                        *cmd++ = val;
                }

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index cb9eef1635e10fba799dfe7d155354387a2cff33..294c58aba2c152a8f106da91c55d5c11794b13d2 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
                *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
                *cs++ = v;
        } else if (INTEL_GEN(i915) >= 4) {
-               *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
+               *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
                *cs++ = 0;
                *cs++ = i915_ggtt_offset(vma) + offset;
                *cs++ = v;
        } else {
-               *cs++ = MI_STORE_DWORD_IMM | 1 << 22;
+               *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
                *cs++ = i915_ggtt_offset(vma) + offset;
                *cs++ = v;
                *cs++ = MI_NOOP;

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 0d8e719802fa2b07b3d8be0fa65d301a99dc68f2..65100d3e31cffcb304ea412e6466f1b663529dc7 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
                        *cmd++ = value;
                } else if (gen >= 4) {
                        *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
-                               (gen < 6 ? 1 << 22 : 0);
+                               (gen < 6 ? MI_USE_GGTT : 0);
                        *cmd++ = 0;
                        *cmd++ = offset;
                        *cmd++ = value;
                } else {
-                       *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+                       *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
                        *cmd++ = offset;
                        *cmd++ = value;
                }

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 5cb808dc5b5000b54f46dedeb8e192f8b1bb71d5..0fc6da81f86e2518268f09044fc507f946b22dfe 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h,
                *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
                *batch++ = lower_32_bits(vma->node.start);
        } else if (INTEL_GEN(i915) >= 4) {
-               *batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
+               *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
                *batch++ = 0;
                *batch++ = lower_32_bits(hws_address(hws, rq));
                *batch++ = rq->fence.seqno;