reg = <0>;
spi-max-frequency = <24000000>;
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- MIBIB@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- QSEE@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- CDT@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- DDRPARAMS@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- APPSBLENV@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- APPSBL@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- ART@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+
+ firmware@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x180000 0x1e80000>;
+ };
};
};
};