writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
}
-void config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
{
- writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
- writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
- writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
- writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
- writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
+ writel(val, &ioctrl_reg->cm0ioctl);
+ writel(val, &ioctrl_reg->cm1ioctl);
+ writel(val, &ioctrl_reg->cm2ioctl);
+ writel(val, &ioctrl_reg->dt0ioctl);
+ writel(val, &ioctrl_reg->dt1ioctl);
}
void config_ddr(short ddr_type)
{
- struct ddr_ioctrl ioctrl;
-
enable_emif_clocks();
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
- ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
-
- config_io_ctrl(&ioctrl);
+ config_io_ctrl(DDR2_IOCTRL_VALUE);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
unsigned int dt1ioctl;
};
-/**
- * Encapsulates DDR CMD & DATA io control registers.
- */
-struct ddr_ioctrl {
- unsigned long cmd1ctl;
- unsigned long cmd2ctl;
- unsigned long cmd3ctl;
- unsigned long data1ctl;
- unsigned long data2ctl;
-};
-
/**
* Configure DDR io control registers
*/
-void config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
struct ddr_ctrl {
unsigned int ddrioctrl;