am33xx: Rework config_io_ctrl slightly
authorTom Rini <trini@ti.com>
Tue, 24 Jul 2012 23:31:26 +0000 (16:31 -0700)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:12 +0000 (14:58 +0200)
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/include/asm/arch-am33xx/ddr_defs.h

index 993f3da00748738016fa4cf0078b436197f85710..597d62f61ba34288d17d34b590a43be3167600e9 100644 (file)
@@ -120,11 +120,11 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
        writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
-void config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
 {
-       writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
-       writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
-       writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
-       writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
-       writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
+       writel(val, &ioctrl_reg->cm0ioctl);
+       writel(val, &ioctrl_reg->cm1ioctl);
+       writel(val, &ioctrl_reg->cm2ioctl);
+       writel(val, &ioctrl_reg->dt0ioctl);
+       writel(val, &ioctrl_reg->dt1ioctl);
 }
index 0190ec65e7ca7b73078c344b2b345c3de517f61f..3219045447eb201233dc601dd37b0384060dd43c 100644 (file)
@@ -116,8 +116,6 @@ static void config_vtp(void)
 
 void config_ddr(short ddr_type)
 {
-       struct ddr_ioctrl ioctrl;
-
        enable_emif_clocks();
 
        if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
@@ -132,13 +130,7 @@ void config_ddr(short ddr_type)
                writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
                writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 
-               ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
-               ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
-               ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
-               ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
-               ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
-
-               config_io_ctrl(&ioctrl);
+               config_io_ctrl(DDR2_IOCTRL_VALUE);
 
                /* Set CKE to be controlled by EMIF/DDR PHY */
                writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
index 7806e1b929a79a3a65c12ef00e8b24a1f1c797db..ebd3077f72ffe3ac98f1f63f8baab793025c2be9 100644 (file)
@@ -173,21 +173,10 @@ struct ddr_cmdtctrl {
        unsigned int dt1ioctl;
 };
 
-/**
- * Encapsulates DDR CMD & DATA io control registers.
- */
-struct ddr_ioctrl {
-       unsigned long cmd1ctl;
-       unsigned long cmd2ctl;
-       unsigned long cmd3ctl;
-       unsigned long data1ctl;
-       unsigned long data2ctl;
-};
-
 /**
  * Configure DDR io control registers
  */
-void config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
 
 struct ddr_ctrl {
        unsigned int ddrioctrl;