};
#endif
+/*
+ * known 6345 boards
+ */
+#ifdef CONFIG_BCM63XX_CPU_6345
+static struct board_info __initdata board_96345gw2 = {
+ .name = "96345GW2",
+ .expected_cpu_id = 0x6345,
+};
+#endif
+
/*
* known 6348 boards
*/
&board_96338gw,
&board_96338w,
#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+ &board_96345gw2,
+#endif
#ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r,
&board_96348gw,
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
u32 val;
+ if (BCMCPU_IS_6345())
+ return (8 * 1024 * 1024);
+
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
val = bcm_sdram_readl(SDRAM_CFG_REG);
rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
/* disable all hardware blocks clock for now */
if (BCMCPU_IS_6338())
mask = CKCTL_6338_ALL_SAFE_EN;
- else if (BCMCPU_IS_6345())
- mask = CKCTL_6345_UART_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ALL_SAFE_EN;
else