return 0;
}
-int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *val)
+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
{
u32 data = 0;
return PCIBIOS_SUCCESSFUL;
}
-int pci_config_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
{
u32 data = 0;
return PCIBIOS_SUCCESSFUL;
}
-struct pci_ops rt2880_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
+static struct pci_ops rt2880_pci_ops = {
+ .read = rt2880_pci_config_read,
+ .write = rt2880_pci_config_write,
};
-static struct resource pci_io_resource = {
- .name = "pci MEM space",
+static struct resource rt2880_pci_io_resource = {
+ .name = "PCI MEM space",
.start = 0x20000000,
.end = 0x2FFFFFFF,
.flags = IORESOURCE_MEM,
};
-static struct resource pci_mem_resource = {
- .name = "pci IO space",
+static struct resource rt2880_pci_mem_resource = {
+ .name = "PCI IO space",
.start = 0x00460000,
.end = 0x0046FFFF,
.flags = IORESOURCE_IO,
};
-struct pci_controller rt2880_controller = {
+static struct pci_controller rt2880_pci_controller = {
.pci_ops = &rt2880_pci_ops,
- .mem_resource = &pci_io_resource,
- .io_resource = &pci_mem_resource,
- .mem_offset = 0x00000000UL,
- .io_offset = 0x00000000UL,
+ .mem_resource = &rt2880_pci_io_resource,
+ .io_resource = &rt2880_pci_mem_resource,
};
void inline read_config(unsigned long bus, unsigned long dev,
return irq;
}
-int init_rt2880pci(void)
+static int __init rt2880_pci_init(void)
{
unsigned long val = 0;
int i;
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
- register_pci_controller(&rt2880_controller);
+ register_pci_controller(&rt2880_pci_controller);
return 0;
}
{0}
};
-arch_initcall(init_rt2880pci);
+arch_initcall(rt2880_pci_init);