switch (bcm63xx_cpu_id) {
case BCM3368_CPU_ID:
-@@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void)
+@@ -400,6 +442,16 @@ void __init bcm63xx_cpu_init(void)
/* BCM6369 is a BCM6368 without xDSL, so treat it the same */
bcm63xx_cpu_id = BCM6368_CPU_ID;
break;
++ case BCM63167_CPU_ID:
+ case BCM63168_CPU_ID:
+ case BCM63169_CPU_ID:
+ case BCM63268_CPU_ID:
return 0;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -22,6 +22,10 @@
+@@ -22,6 +22,11 @@
#define BCM6362_CPU_ID 0x6362
#define BCM6368_CPU_ID 0x6368
#define BCM6369_CPU_ID 0x6369
++#define BCM63167_CPU_ID 0x63167
+#define BCM63168_CPU_ID 0x63168
+#define BCM63169_CPU_ID 0x63169
+#define BCM63268_CPU_ID 0x63268
void __init bcm63xx_cpu_init(void);
u32 bcm63xx_get_cpu_variant(void);
-@@ -62,6 +66,10 @@ static inline u32 __pure __bcm63xx_get_c
+@@ -62,6 +67,10 @@ static inline u32 __pure __bcm63xx_get_c
#ifdef CONFIG_BCM63XX_CPU_6368
case BCM6368_CPU_ID:
#endif
break;
default:
unreachable();
-@@ -87,6 +95,7 @@ static inline u32 __pure bcm63xx_get_cpu
+@@ -87,6 +96,7 @@ static inline u32 __pure bcm63xx_get_cpu
#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
#define BCMCPU_VARIANT_IS_3368() \
(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
-@@ -110,6 +119,14 @@ static inline u32 __pure bcm63xx_get_cpu
+@@ -110,6 +120,16 @@ static inline u32 __pure bcm63xx_get_cpu
(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
#define BCMCPU_VARIANT_IS_6369() \
(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
++#define BCMCPU_VARIANT_IS_63167() \
++ (bcm63xx_get_cpu_variant() == BCM63167_CPU_ID)
+#define BCMCPU_VARIANT_IS_63168() \
+ (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
+#define BCMCPU_VARIANT_IS_63169() \
/*
* While registers sets are (mostly) the same across 63xx CPU, base
-@@ -574,6 +591,52 @@ enum bcm63xx_regs_set {
+@@ -574,6 +594,52 @@ enum bcm63xx_regs_set {
#define BCM_6368_RNG_BASE (0xb0004180)
#define BCM_6368_MISC_BASE (0xdeadbeef)
extern const unsigned long *bcm63xx_regs_base;
-@@ -1042,6 +1105,73 @@ enum bcm63xx_irq {
+@@ -1042,6 +1108,73 @@ enum bcm63xx_irq {
#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
#define BCM6328_CPU_ID 0x6328
#define BCM63281_CPU_ID 0x63281
#define BCM63283_CPU_ID 0x63283
-@@ -39,6 +40,10 @@ static inline u32 __pure __bcm63xx_get_c
+@@ -40,6 +41,10 @@ static inline u32 __pure __bcm63xx_get_c
case BCM3368_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
case BCM6328_CPU_ID:
#endif
-@@ -88,6 +93,7 @@ static inline u32 __pure bcm63xx_get_cpu
+@@ -89,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
}
#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
-@@ -99,6 +105,8 @@ static inline u32 __pure bcm63xx_get_cpu
+@@ -100,6 +106,8 @@ static inline u32 __pure bcm63xx_get_cpu
#define BCMCPU_VARIANT_IS_3368() \
(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
#define BCMCPU_VARIANT_IS_63281() \
(bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
#define BCMCPU_VARIANT_IS_63283() \
-@@ -253,6 +261,56 @@ enum bcm63xx_regs_set {
+@@ -256,6 +264,56 @@ enum bcm63xx_regs_set {
#define BCM_3368_MISC_BASE (0xdeadbeef)
/*
* 6328 register sets base address
*/
#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
-@@ -775,6 +833,55 @@ enum bcm63xx_irq {
+@@ -778,6 +836,55 @@ enum bcm63xx_irq {
#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -181,7 +181,8 @@ enum bcm63xx_regs_set {
+@@ -184,7 +184,8 @@ enum bcm63xx_regs_set {
RSET_PCMDMAC,
RSET_PCMDMAS,
RSET_RNG,
};
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
-@@ -259,6 +260,7 @@ enum bcm63xx_regs_set {
+@@ -262,6 +263,7 @@ enum bcm63xx_regs_set {
#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
#define BCM_3368_RNG_BASE (0xdeadbeef)
#define BCM_3368_MISC_BASE (0xdeadbeef)
/*
* 6318 register sets base address
-@@ -306,6 +308,7 @@ enum bcm63xx_regs_set {
+@@ -309,6 +311,7 @@ enum bcm63xx_regs_set {
#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6318_RNG_BASE (0xdeadbeef)
#define BCM_6318_MISC_BASE (0xb0000280)
#define BCM_6318_OTP_BASE (0xdeadbeef)
#define BCM_6318_STRAP_BASE (0xb0000900)
-@@ -356,6 +359,7 @@ enum bcm63xx_regs_set {
+@@ -359,6 +362,7 @@ enum bcm63xx_regs_set {
#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6328_RNG_BASE (0xdeadbeef)
#define BCM_6328_MISC_BASE (0xb0001800)
#define BCM_6328_OTP_BASE (0xb0000600)
/*
-@@ -405,6 +409,7 @@ enum bcm63xx_regs_set {
+@@ -408,6 +412,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6338_RNG_BASE (0xdeadbeef)
#define BCM_6338_MISC_BASE (0xdeadbeef)
/*
* 6345 register sets base address
-@@ -453,6 +458,7 @@ enum bcm63xx_regs_set {
+@@ -456,6 +461,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6345_RNG_BASE (0xdeadbeef)
#define BCM_6345_MISC_BASE (0xdeadbeef)
/*
* 6348 register sets base address
-@@ -499,6 +505,7 @@ enum bcm63xx_regs_set {
+@@ -502,6 +508,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6348_RNG_BASE (0xdeadbeef)
#define BCM_6348_MISC_BASE (0xdeadbeef)
/*
* 6358 register sets base address
-@@ -545,7 +552,7 @@ enum bcm63xx_regs_set {
+@@ -548,7 +555,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
#define BCM_6358_RNG_BASE (0xdeadbeef)
#define BCM_6358_MISC_BASE (0xdeadbeef)
/*
* 6362 register sets base address
-@@ -593,6 +600,7 @@ enum bcm63xx_regs_set {
+@@ -596,6 +603,7 @@ enum bcm63xx_regs_set {
#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6362_RNG_BASE (0xdeadbeef)
#define BCM_6362_MISC_BASE (0xb0001800)
#define BCM_6362_NAND_REG_BASE (0xb0000200)
#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
-@@ -648,6 +656,7 @@ enum bcm63xx_regs_set {
+@@ -651,6 +659,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
#define BCM_6368_RNG_BASE (0xb0004180)
#define BCM_6368_MISC_BASE (0xdeadbeef)
/*
* 63268 register sets base address
-@@ -695,6 +704,7 @@ enum bcm63xx_regs_set {
+@@ -698,6 +707,7 @@ enum bcm63xx_regs_set {
#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
#define BCM_63268_RNG_BASE (0xdeadbeef)
#define BCM_63268_MISC_BASE (0xb0001800)
extern const unsigned long *bcm63xx_regs_base;
-@@ -740,6 +750,7 @@ extern const unsigned long *bcm63xx_regs
+@@ -743,6 +753,7 @@ extern const unsigned long *bcm63xx_regs
[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \