#include <linux/spi/spi.h>
#include <asm/hardware.h>
-#include <asm/irq.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/system.h>
#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
+#include <linux/irq.h>
#include <asm/hardware.h>
-#include <asm/irq.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
{
unsigned int i;
- /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
+ /* configure IRQ's */
+ for (i = 0; i < NR_IRQS; i++) {
+ set_irq_flags(i, IRQF_VALID);
+ set_irq_chip(i, &pnx4008_irq_chip);
+ pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
+ }
+
+ /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
+ /* mask all others */
__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
INTC_ER(MAIN_BASE_INT));
__raw_writel(0, INTC_ER(SIC1_BASE_INT));
__raw_writel(0, INTC_ER(SIC2_BASE_INT));
-
- /* configure all other IRQ's */
- for (i = 0; i < NR_IRQS; i++) {
- if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
- i == SUB2_IRQ_N || i == SUB1_IRQ_N)
- continue;
- set_irq_flags(i, IRQF_VALID);
- set_irq_chip(i, &pnx4008_irq_chip);
- pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
- }
}
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/irq.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/leds.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
#include <asm/mach/time.h>
-
-#include <linux/time.h>
-#include <linux/timex.h>
#include <asm/errno.h>
/*! Note: all timers are UPCOUNTING */