PCI: generic: Add support for Synopsys DesignWare RC in ECAM mode

Some implementations of the Synopsys DesignWare PCIe controller implement
a so-called ECAM shift mode, which allows a static memory window to be
configured that covers the configuration space of the entire bus range.

Usually, when the firmware performs all the low level configuration that is
required to expose this controller in a fully ECAM compatible manner, we
can simply describe it as "pci-host-ecam-generic" and be done with it.
However, in some cases (e.g., the Marvell Armada 80x0 as well as the
Socionext SynQuacer Soc), the IP was synthesized with an ATU window
granularity that does not allow the first bus to be mapped in a way that
prevents the device on the downstream port from appearing more than once,
and so we still need special handling in software to drive this static
almost-ECAM configuration.

So extend the pci-host-generic driver so it can support these controllers
as well, by adding special config space accessors that take the above quirk
into account.

Note that, unlike most drivers for this IP, this driver does not expose a
fake bridge device at B/D/F 00:00.0. There is no point in doing so, given
that this is not a true bridge, and does not require any windows to be
configured in order for the downstream device to operate correctly.
Omitting it also prevents the PCI resource allocation routines from handing
out BAR space to it unnecessarily.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[bhelgaas: factor out pci_dw_valid_device(), add pci_dw_ecam_map_bus() and
use generic read/write functions]
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Acked-by: Will Deacon <will.deacon@arm.com>

diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
index 7d709a7e0aa8a7cf2e0bc55de059f1731d8adb27..2f05511ce718c147736927a0c3f76dae8c999140 100644 (file)
--- a/drivers/pci/host/pci-host-generic.c
+++ b/drivers/pci/host/pci-host-generic.c
@@ -35,6 +35,40 @@ static struct pci_ecam_ops gen_pci_cfg_cam_bus_ops = {
        }
 };
 
+static bool pci_dw_valid_device(struct pci_bus *bus, unsigned int devfn)
+{
+       struct pci_config_window *cfg = bus->sysdata;
+
+       /*
+        * The Synopsys DesignWare PCIe controller in ECAM mode will not filter
+        * type 0 config TLPs sent to devices 1 and up on its downstream port,
+        * resulting in devices appearing multiple times on bus 0 unless we
+        * filter out those accesses here.
+        */
+       if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0)
+               return false;
+
+       return true;
+}
+
+static void __iomem *pci_dw_ecam_map_bus(struct pci_bus *bus,
+                                        unsigned int devfn, int where)
+{
+       if (!pci_dw_valid_device(bus, devfn))
+               return NULL;
+
+       return pci_ecam_map_bus(bus, devfn, where);
+}
+
+static struct pci_ecam_ops pci_dw_ecam_bus_ops = {
+       .bus_shift      = 20,
+       .pci_ops        = {
+               .map_bus        = pci_dw_ecam_map_bus,
+               .read           = pci_generic_config_read,
+               .write          = pci_generic_config_write,
+       }
+};
+
 static const struct of_device_id gen_pci_of_match[] = {
        { .compatible = "pci-host-cam-generic",
          .data = &gen_pci_cfg_cam_bus_ops },
@@ -42,6 +76,15 @@ static const struct of_device_id gen_pci_of_match[] = {
        { .compatible = "pci-host-ecam-generic",
          .data = &pci_generic_ecam_ops },
 
+       { .compatible = "marvell,armada8k-pcie-ecam",
+         .data = &pci_dw_ecam_bus_ops },
+
+       { .compatible = "socionext,synquacer-pcie-ecam",
+         .data = &pci_dw_ecam_bus_ops },
+
+       { .compatible = "snps,dw-pcie-ecam",
+         .data = &pci_dw_ecam_bus_ops },
+
        { },
 };