clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks

The PDMA{0,1} and EPLL clock IDs are added separately in this
patch so the patch can be merged to the arm-soc tree as dependency.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 85b467b3a20718be416386713b6b362d67c5b02b..6cb4e90f81fc33628d23f353cbbd6cba00815945 100644 (file)
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -19,6 +19,7 @@
 #define CLK_FOUT_MPLL          4
 #define CLK_FOUT_BPLL          5
 #define CLK_FOUT_KPLL          6
+#define CLK_FOUT_EPLL          7
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_UART0         128
@@ -55,6 +56,8 @@
 #define CLK_MMC0               351
 #define CLK_MMC1               352
 #define CLK_MMC2               353
+#define CLK_PDMA0              362
+#define CLK_PDMA1              363
 #define CLK_USBH20             365
 #define CLK_USBD300            366
 #define CLK_USBD301            367