rt2x00: Fix RT3572 channel switch RFCSR 7 programming.
authorGertjan van Wingerde <gwingerde@gmail.com>
Mon, 6 Feb 2012 22:45:12 +0000 (23:45 +0100)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 8 Feb 2012 20:26:31 +0000 (15:26 -0500)
Align with the v2.5.0.0 Ralink RT3572 driver.

Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com>
Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
Acked-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/rt2x00/rt2800.h
drivers/net/wireless/rt2x00/rt2800lib.c

index 8aabd0dc02c338203acb7817904ba35806bd1a5c..c6648b02bf8154ebd943090e44de92b3097402f6 100644 (file)
@@ -1819,10 +1819,12 @@ struct mac_iveiv_entry {
  * RFCSR 7:
  */
 #define RFCSR7_RF_TUNING               FIELD8(0x01)
-#define RFCSR7_R02                             FIELD8(0x07)
-#define RFCSR7_R3                              FIELD8(0x08)
-#define RFCSR7_R45                             FIELD8(0x30)
-#define RFCSR7_R67                             FIELD8(0xc0)
+#define RFCSR7_BIT1                    FIELD8(0x02)
+#define RFCSR7_BIT2                    FIELD8(0x04)
+#define RFCSR7_BIT3                    FIELD8(0x08)
+#define RFCSR7_BIT4                    FIELD8(0x10)
+#define RFCSR7_BIT5                    FIELD8(0x20)
+#define RFCSR7_BITS67                  FIELD8(0xc0)
 
 /*
  * RFCSR 11:
index 135e8a40edd3a49445edb35187771abc1c0142e6..395453c41e234830f07e1ec42c5bf0ac5dbecf46 100644 (file)
@@ -1865,7 +1865,12 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
                rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
                rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
        } else {
-               rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
+               rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
+               rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
                rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
                rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
                rt2800_rfcsr_write(rt2x00dev, 11, 0x00);