return ret;
}
-EXPORT_SYMBOL(mxc_iomux_mode);
/*
* This function configures the pad value for a IOMUX pin.
spin_unlock(&gpio_mux_lock);
}
-EXPORT_SYMBOL(mxc_iomux_set_pad);
/*
* allocs a single pin:
return 0;
}
-EXPORT_SYMBOL(mxc_iomux_alloc_pin);
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
const char *label)
mxc_iomux_release_multiple_pins(pin_list, i);
return ret;
}
-EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
void mxc_iomux_release_pin(unsigned int pin)
{
if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map);
}
-EXPORT_SYMBOL(mxc_iomux_release_pin);
void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
{
p++;
}
}
-EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
/*
* This function enables/disables the general purpose function for a particular
__raw_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock);
}
-EXPORT_SYMBOL(mxc_iomux_set_gpr);
return 0;
}
-EXPORT_SYMBOL(mxc_gpio_mode);
static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
{
ret = imx_iomuxv1_setup_multiple(pin_list, count);
return ret;
}
-EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
int __init imx_iomuxv1_init(void __iomem *base, int numports)
{
return 0;
}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
{
}
return 0;
}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{