drm/amdkfd: Fix gfx9 XNACK state save/restore

SQ_WAVE_IB_STS.RCNT grew from 4 bits to 5 in gfx9. Do not truncate
when saving in the high bits of TTMP1.

Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 097da0dd3b04b04c1506ac25cf19f300c62e8346..eed845b4e9a76d2688cdc85dce0878ba2309e345 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -310,8 +310,8 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
        0xbe801f6c, 0x866dff6d,
        0x0000ffff, 0xbef00080,
        0xb9700283, 0xb8f02407,
-       0x8e709c70, 0x876d706d,
-       0xb8f003c7, 0x8e709b70,
+       0x8e709b70, 0x876d706d,
+       0xb8f003c7, 0x8e709a70,
        0x876d706d, 0xb8f0f807,
        0x8670ff70, 0x00007fff,
        0xb970f807, 0xbeee007e,
@@ -549,11 +549,11 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
        0x00000048, 0xc0031e77,
        0x00000058, 0xc0071eb7,
        0x0000005c, 0xbf8cc07f,
-       0x866fff6d, 0xf0000000,
-       0x8f6f9c6f, 0x8e6f906f,
+       0x866fff6d, 0xf8000000,
+       0x8f6f9b6f, 0x8e6f906f,
        0xbeee0080, 0x876e6f6e,
-       0x866fff6d, 0x08000000,
-       0x8f6f9b6f, 0x8e6f8f6f,
+       0x866fff6d, 0x04000000,
+       0x8f6f9a6f, 0x8e6f8f6f,
        0x876e6f6e, 0x866fff70,
        0x00800000, 0x8f6f976f,
        0xb96ef807, 0x866dff6d,

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
index 6a010c9e55deb15832a5b45f4064fc5bb5ff1cf3..e1ac345176424aa7310e8319b03a476efdbbbb36 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
@@ -150,10 +150,10 @@ var S_SAVE_SPI_INIT_MTYPE_SHIFT           =   28
 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK    =   0x04000000          //bit[26]: FirstWaveInTG
 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT   =   26
 
-var S_SAVE_PC_HI_RCNT_SHIFT            =   28                  //FIXME  check with Brian to ensure all fields other than PC[47:0] can be used
-var S_SAVE_PC_HI_RCNT_MASK             =   0xF0000000          //FIXME
-var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT    =   27                  //FIXME
-var S_SAVE_PC_HI_FIRST_REPLAY_MASK     =   0x08000000          //FIXME
+var S_SAVE_PC_HI_RCNT_SHIFT            =   27                  //FIXME  check with Brian to ensure all fields other than PC[47:0] can be used
+var S_SAVE_PC_HI_RCNT_MASK             =   0xF8000000          //FIXME
+var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT    =   26                  //FIXME
+var S_SAVE_PC_HI_FIRST_REPLAY_MASK     =   0x04000000          //FIXME
 
 var s_save_spi_init_lo             =   exec_lo
 var s_save_spi_init_hi             =   exec_hi