static u8 hwctl = 0;
-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+ if (hwctl & 0x1) {
+ WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+ } else if (hwctl & 0x2) {
+ WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+ } else {
+ WRITE_NAND(byte, base);
+ }
+}
+
+static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
hwctl &= ~0x2;
}
if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
- if (hwctl & 0x1) {
- WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
- } else if (hwctl & 0x2) {
- WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
- } else {
- WRITE_NAND(byte, base);
- }
+ upmnand_write_byte (mtd, cmd);
}
static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
nand->cmd_ctrl = upmnand_hwcontrol;
nand->read_byte = upmnand_read_byte;
- nand->write_byte = upmnand_write_byte;
nand->dev_ready = tqm8272_dev_ready;
#ifndef CONFIG_NAND_SPL