net: qcom/emac: optimize QDF2400 SGMII RX/TX impedence values

Adjust the impedance values of the RX and TX lanes in the SGMII block
so that they are closer to optimal values.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c b/drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
index f62c215be779853ad76cf71f02b09dc4f7d62a1a..7116be485e6129090b2a60f6a8397a37be3b1897 100644 (file)
--- a/drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
+++ b/drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
@@ -26,6 +26,7 @@
 
 /* SGMII digital lane registers */
 #define EMAC_SGMII_LN_DRVR_CTRL0               0x000C
+#define EMAC_SGMII_LN_DRVR_CTRL1               0x0010
 #define EMAC_SGMII_LN_DRVR_TAP_EN              0x0018
 #define EMAC_SGMII_LN_TX_MARGINING             0x001C
 #define EMAC_SGMII_LN_TX_PRE                   0x0020
@@ -48,6 +49,7 @@
 #define EMAC_SGMII_LN_RX_EN_SIGNAL             0x02AC
 #define EMAC_SGMII_LN_RX_MISC_CNTRL0           0x02B8
 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV                0x02C8
+#define EMAC_SGMII_LN_RX_RESECODE_OFFSET       0x02CC
 
 /* SGMII digital lane register values */
 #define UCDR_STEP_BY_TWO_MODE0                 BIT(7)
@@ -73,6 +75,8 @@
 #define CML_GEAR_MODE(x)                       (((x) & 7) << 3)
 #define CML2CMOS_IBOOST_MODE(x)                        ((x) & 7)
 
+#define RESCODE_OFFSET(x)                      ((x) & 0x1f)
+
 #define MIXER_LOADB_MODE(x)                    (((x) & 0xf) << 2)
 #define MIXER_DATARATE_MODE(x)                 ((x) & 3)
 
@@ -159,6 +163,8 @@ static const struct emac_reg_write sgmii_laned[] = {
        {EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
        {EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(1)},
        {EMAC_SGMII_LN_RX_BAND, BAND_MODE0(2)},
+       {EMAC_SGMII_LN_DRVR_CTRL1, RESCODE_OFFSET(7)},
+       {EMAC_SGMII_LN_RX_RESECODE_OFFSET, RESCODE_OFFSET(9)},
        {EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
        {EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(2) |
                EN_DLL_MODE0 | EN_IQ_DCC_MODE0 | EN_IQCAL_MODE0},