added dmabounce debug code to ixp4xx

SVN-Revision: 10240

diff --git a/target/linux/ixp4xx/config-default b/target/linux/ixp4xx/config-default
index 1b725f646b9067ac3554fab06420498b48ec6f56..9673dc75bc54dba2fa01ace47c3983c9b9b566a6 100644 (file)
--- a/target/linux/ixp4xx/config-default
+++ b/target/linux/ixp4xx/config-default
@@ -85,6 +85,7 @@ CONFIG_DLCI_COUNT=24
 CONFIG_DLCI_MAX=8
 # CONFIG_DM9000 is not set
 CONFIG_DMABOUNCE=y
+CONFIG_DMABOUNCE_DEBUG=y
 CONFIG_DNOTIFY=y
 # CONFIG_DSCC4 is not set
 # CONFIG_E100 is not set

diff --git a/target/linux/ixp4xx/patches-2.6.23/400-dmabounce.patch b/target/linux/ixp4xx/patches-2.6.23/400-dmabounce.patch
new file mode 100644 (file)
index 0000000..481b443
--- /dev/null
+++ b/target/linux/ixp4xx/patches-2.6.23/400-dmabounce.patch
@@ -0,0 +1,31 @@
+Index: linux-2.6.23.14/arch/arm/common/dmabounce.c
+===================================================================
+--- linux-2.6.23.14.orig/arch/arm/common/dmabounce.c   2008-01-24 22:03:28.475500801 +0100
++++ linux-2.6.23.14/arch/arm/common/dmabounce.c        2008-01-24 22:17:36.415822168 +0100
+@@ -116,6 +116,10 @@
+       } else if (size <= device_info->large.size) {
+               pool = &device_info->large;
+       } else {
++#ifdef CONFIG_DMABOUNCE_DEBUG
++              printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size);
++              dump_stack();
++#endif
+               pool = NULL;
+       }
+ 
+Index: linux-2.6.23.14/arch/arm/mach-ixp4xx/Kconfig
+===================================================================
+--- linux-2.6.23.14.orig/arch/arm/mach-ixp4xx/Kconfig  2008-01-24 22:10:29.331484012 +0100
++++ linux-2.6.23.14/arch/arm/mach-ixp4xx/Kconfig       2008-01-24 22:11:42.891675973 +0100
+@@ -220,6 +220,11 @@
+       default y
+       depends on PCI
+ 
++config DMABOUNCE_DEBUG
++      bool "Enable DMABounce debuging"
++      default n
++      depends DMABOUNCE
++
+ config IXP4XX_INDIRECT_PCI
+       bool "Use indirect PCI memory access"
+       depends on PCI