Changes for U-Boot 1.1.4:
======================================================================
+* Add support for Ocotea pass 3 with 440GX Rev. F
+ Patch by Stefan Roese, 01 Nov 2005
+
* Fix external IRQ configuration on Yellowstone & Yosemite
Patch by Stefan Roese, 28 Oct 2005
}
}
+ /*
+ * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
+ */
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
+ out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
+ }
+
/* Turn off the LED's */
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
#define FPGA_REG2_EXT_INTFACE_MASK 0x04
#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
+#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/
#define FPGA_REG2_DEFAULT_UART1_N 0x01
#define FPGA_REG3 (CFG_FPGA_BASE + 0x03)
#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
case PVR_440GX_RC:
puts("GX Rev. C");
break;
+ case PVR_440GX_RF:
+ puts("GX Rev. F");
+ break;
case PVR_440EP_RA:
puts("EP Rev. A");
break;
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892
+#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
#define PVR_601 0x00010000
#define PVR_602 0x00050000