return ret;
}
- /* Remove all resets to allow NIC to operate */
- iwl_write32(priv, CSR_RESET, 0);
+ trans_kick_nic(priv);
/*
* Some things may run in the background now, but we
* @send_cmd_pdu:send a host command: flags can be CMD_*
* @get_tx_cmd: returns a pointer to a new Tx cmd for the upper layer use
* @tx: send an skb
+ * @kick_nic: remove the RESET from the embedded CPU and let it run
* @sync_irq: the upper layer will typically disable interrupt and call this
* handler. After this handler returns, it is guaranteed that all
* the ISR / tasklet etc... have finished running and the transport
struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
struct iwl_rxon_context *ctx);
+ void (*kick_nic)(struct iwl_priv *priv);
+
void (*sync_irq)(struct iwl_priv *priv);
void (*free)(struct iwl_priv *priv);
};
return 0;
}
+static void iwl_trans_kick_nic(struct iwl_priv *priv)
+{
+ /* Remove all resets to allow NIC to operate */
+ iwl_write32(priv, CSR_RESET, 0);
+}
+
static void iwl_trans_sync_irq(struct iwl_priv *priv)
{
/* wait to make sure we flush pending tasklet*/
.get_tx_cmd = iwl_trans_get_tx_cmd,
.tx = iwl_trans_tx,
+ .kick_nic = iwl_trans_kick_nic,
.sync_irq = iwl_trans_sync_irq,
.free = iwl_trans_free,
return priv->trans.ops->tx(priv, skb, tx_cmd, txq_id, fc, ampdu, ctx);
}
+static inline void trans_kick_nic(struct iwl_priv *priv)
+{
+ priv->trans.ops->kick_nic(priv);
+}
+
static inline void trans_sync_irq(struct iwl_priv *priv)
{
priv->trans.ops->sync_irq(priv);