AT91SAM9263EK: hook up the ATMEL LCD driver

This patch makes the necessary adaptations (PIO configurations and
defines in config header file) to hook up the Atmel LCD driver to the
AT91SAM9263EK board.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index a6268a6d87e107686831de1c69314a3752546048..ba7fc71d75e70ad715ad3f358695a36fa90fa937 100644 (file)
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/sizes.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91sam9263_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -30,6 +31,8 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -193,6 +196,65 @@ static void at91sam9263ek_uhp_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+       vl_col:         240,
+       vl_row:         320,
+       vl_clk:         4965000,
+       vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
+                       ATMEL_LCDC_INVFRAME_INVERTED,
+       vl_bpix:        3,
+       vl_tft:         1,
+       vl_hsync_len:   5,
+       vl_left_margin: 1,
+       vl_right_margin:33,
+       vl_vsync_len:   1,
+       vl_upper_margin:1,
+       vl_lower_margin:0,
+       mmio:           AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
+}
+
+void lcd_disable(void)
+{
+       at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
+}
+
+static void at91sam9263ek_lcd_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
+       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
+       at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
+       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
+       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
+       at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
+       at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
+       at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
+       at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
+       at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
+       at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
+       at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
+       at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
+       at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
+       at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
+       at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
+       at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
+       at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
+       at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
+
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+       gd->fb_base = AT91SAM9263_SRAM0_BASE;
+}
+#endif
+
 int board_init(void)
 {
        /* Enable Ctrlc */
@@ -215,6 +277,9 @@ int board_init(void)
 #endif
 #ifdef CONFIG_USB_OHCI_NEW
        at91sam9263ek_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+       at91sam9263ek_lcd_hw_init();
 #endif
        return 0;
 }

diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d28f7d8aaba7c193c454c5c2c045e95f71bed2bd..1c50134cd5e36afea7d224165a43c7662a065230 100644 (file)
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -28,6 +28,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
+#define AT91_CPU_NAME          "AT91SAM9263"
 #define AT91_MAIN_CLOCK                199919000       /* from 16.367 MHz crystal */
 #define AT91_MASTER_CLOCK      99959500        /* peripheral = main / 2 */
 #define CFG_HZ                 1000000         /* 1us resolution */
@@ -55,6 +56,18 @@
 #undef CONFIG_USART2
 #define CONFIG_USART3          1       /* USART 3 is DBGU */
 
+/* LCD */
+#define CONFIG_LCD                     1
+#define LCD_BPP                                LCD_COLOR8
+#define CONFIG_LCD_LOGO                        1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO                        1
+#define CONFIG_LCD_INFO_BELOW_LOGO     1
+#define CFG_WHITE_ON_BLACK             1
+#define CONFIG_ATMEL_LCD               1
+#define CONFIG_ATMEL_LCD_BGR555                1
+#define CFG_CONSOLE_IS_IN_ENV          1
+
 #define CONFIG_BOOTDELAY       3
 
 /* #define CONFIG_ENV_OVERWRITE        1 */