drm/msm/hdmi: Update generated headers to split PHY/PLL offsets

- Create separate domains for 8960 PHY and PLL
- Create separate domains for 8x60 PHY

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 10c45700aefedd8800ab0be9d65e6a1da4d0f9b6..a542549a1adc988a804f39720cf4b9ca243e304d 100644 (file)
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -8,17 +8,8 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2015-05-20 20:03:07)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2015-09-18 12:07:28)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  37194 bytes, from 2015-09-18 12:07:28)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  27887 bytes, from 2015-10-22 16:34:52)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2015-10-22 16:35:02)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2015-05-20 20:03:07)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29154 bytes, from 2015-08-10 21:25:43)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-20 20:03:14)
+- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml  (  28770 bytes, from 2015-11-03 11:09:10)
+- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2015-02-09 03:18:10)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -559,7 +550,7 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
 
 #define REG_HDMI_CEC_WR_CHECK_CONFIG                           0x00000370
 
-#define REG_HDMI_8x60_PHY_REG0                                 0x00000300
+#define REG_HDMI_8x60_PHY_REG0                                 0x00000000
 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK                        0x0000001c
 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT               2
 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
@@ -567,7 +558,7 @@ static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
        return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
 }
 
-#define REG_HDMI_8x60_PHY_REG1                                 0x00000304
+#define REG_HDMI_8x60_PHY_REG1                                 0x00000004
 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK                 0x000000f0
 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT                        4
 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
@@ -581,7 +572,7 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
        return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
 }
 
-#define REG_HDMI_8x60_PHY_REG2                                 0x00000308
+#define REG_HDMI_8x60_PHY_REG2                                 0x00000008
 #define HDMI_8x60_PHY_REG2_PD_DESER                            0x00000001
 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1                          0x00000002
 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2                          0x00000004
@@ -591,152 +582,152 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
 #define HDMI_8x60_PHY_REG2_PD_PWRGEN                           0x00000040
 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN                                0x00000080
 
-#define REG_HDMI_8x60_PHY_REG3                                 0x0000030c
+#define REG_HDMI_8x60_PHY_REG3                                 0x0000000c
 #define HDMI_8x60_PHY_REG3_PLL_ENABLE                          0x00000001
 
-#define REG_HDMI_8x60_PHY_REG4                                 0x00000310
+#define REG_HDMI_8x60_PHY_REG4                                 0x00000010
 
-#define REG_HDMI_8x60_PHY_REG5                                 0x00000314
+#define REG_HDMI_8x60_PHY_REG5                                 0x00000014
 
-#define REG_HDMI_8x60_PHY_REG6                                 0x00000318
+#define REG_HDMI_8x60_PHY_REG6                                 0x00000018
 
-#define REG_HDMI_8x60_PHY_REG7                                 0x0000031c
+#define REG_HDMI_8x60_PHY_REG7                                 0x0000001c
 
-#define REG_HDMI_8x60_PHY_REG8                                 0x00000320
+#define REG_HDMI_8x60_PHY_REG8                                 0x00000020
 
-#define REG_HDMI_8x60_PHY_REG9                                 0x00000324
+#define REG_HDMI_8x60_PHY_REG9                                 0x00000024
 
-#define REG_HDMI_8x60_PHY_REG10                                        0x00000328
+#define REG_HDMI_8x60_PHY_REG10                                        0x00000028
 
-#define REG_HDMI_8x60_PHY_REG11                                        0x0000032c
+#define REG_HDMI_8x60_PHY_REG11                                        0x0000002c
 
-#define REG_HDMI_8x60_PHY_REG12                                        0x00000330
+#define REG_HDMI_8x60_PHY_REG12                                        0x00000030
 #define HDMI_8x60_PHY_REG12_RETIMING_EN                                0x00000001
 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN                 0x00000002
 #define HDMI_8x60_PHY_REG12_FORCE_LOCK                         0x00000010
 
-#define REG_HDMI_8960_PHY_REG0                                 0x00000400
+#define REG_HDMI_8960_PHY_REG0                                 0x00000000
 
-#define REG_HDMI_8960_PHY_REG1                                 0x00000404
+#define REG_HDMI_8960_PHY_REG1                                 0x00000004
 
-#define REG_HDMI_8960_PHY_REG2                                 0x00000408
+#define REG_HDMI_8960_PHY_REG2                                 0x00000008
 
-#define REG_HDMI_8960_PHY_REG3                                 0x0000040c
+#define REG_HDMI_8960_PHY_REG3                                 0x0000000c
 
-#define REG_HDMI_8960_PHY_REG4                                 0x00000410
+#define REG_HDMI_8960_PHY_REG4                                 0x00000010
 
-#define REG_HDMI_8960_PHY_REG5                                 0x00000414
+#define REG_HDMI_8960_PHY_REG5                                 0x00000014
 
-#define REG_HDMI_8960_PHY_REG6                                 0x00000418
+#define REG_HDMI_8960_PHY_REG6                                 0x00000018
 
-#define REG_HDMI_8960_PHY_REG7                                 0x0000041c
+#define REG_HDMI_8960_PHY_REG7                                 0x0000001c
 
-#define REG_HDMI_8960_PHY_REG8                                 0x00000420
+#define REG_HDMI_8960_PHY_REG8                                 0x00000020
 
-#define REG_HDMI_8960_PHY_REG9                                 0x00000424
+#define REG_HDMI_8960_PHY_REG9                                 0x00000024
 
-#define REG_HDMI_8960_PHY_REG10                                        0x00000428
+#define REG_HDMI_8960_PHY_REG10                                        0x00000028
 
-#define REG_HDMI_8960_PHY_REG11                                        0x0000042c
+#define REG_HDMI_8960_PHY_REG11                                        0x0000002c
 
-#define REG_HDMI_8960_PHY_REG12                                        0x00000430
+#define REG_HDMI_8960_PHY_REG12                                        0x00000030
 #define HDMI_8960_PHY_REG12_SW_RESET                           0x00000020
 #define HDMI_8960_PHY_REG12_PWRDN_B                            0x00000080
 
-#define REG_HDMI_8960_PHY_REG_BIST_CFG                         0x00000434
+#define REG_HDMI_8960_PHY_REG_BIST_CFG                         0x00000034
 
-#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL                                0x00000438
+#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL                                0x00000038
 
-#define REG_HDMI_8960_PHY_REG_MISC0                            0x0000043c
+#define REG_HDMI_8960_PHY_REG_MISC0                            0x0000003c
 
-#define REG_HDMI_8960_PHY_REG13                                        0x00000440
+#define REG_HDMI_8960_PHY_REG13                                        0x00000040
 
-#define REG_HDMI_8960_PHY_REG14                                        0x00000444
+#define REG_HDMI_8960_PHY_REG14                                        0x00000044
 
-#define REG_HDMI_8960_PHY_REG15                                        0x00000448
+#define REG_HDMI_8960_PHY_REG15                                        0x00000048
 
-#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG                       0x00000500
+#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG                       0x00000000
 
-#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG                    0x00000504
+#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG                    0x00000004
 
-#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0                    0x00000508
+#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0                    0x00000008
 
-#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1                    0x0000050c
+#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1                    0x0000000c
 
-#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG                     0x00000510
+#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG                     0x00000010
 
-#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG                    0x00000514
+#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG                    0x00000014
 
-#define REG_HDMI_8960_PHY_PLL_PWRDN_B                          0x00000518
+#define REG_HDMI_8960_PHY_PLL_PWRDN_B                          0x00000018
 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL                       0x00000002
 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B                  0x00000008
 
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG0                         0x0000051c
+#define REG_HDMI_8960_PHY_PLL_SDM_CFG0                         0x0000001c
 
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG1                         0x00000520
+#define REG_HDMI_8960_PHY_PLL_SDM_CFG1                         0x00000020
 
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG2                         0x00000524
+#define REG_HDMI_8960_PHY_PLL_SDM_CFG2                         0x00000024
 
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG3                         0x00000528
+#define REG_HDMI_8960_PHY_PLL_SDM_CFG3                         0x00000028
 
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG4                         0x0000052c
+#define REG_HDMI_8960_PHY_PLL_SDM_CFG4                         0x0000002c
 
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG0                         0x00000530
+#define REG_HDMI_8960_PHY_PLL_SSC_CFG0                         0x00000030
 
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG1                         0x00000534
+#define REG_HDMI_8960_PHY_PLL_SSC_CFG1                         0x00000034
 
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG2                         0x00000538
+#define REG_HDMI_8960_PHY_PLL_SSC_CFG2                         0x00000038
 
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG3                         0x0000053c
+#define REG_HDMI_8960_PHY_PLL_SSC_CFG3                         0x0000003c
 
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0                     0x00000540
+#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0                     0x00000040
 
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1                     0x00000544
+#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1                     0x00000044
 
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2                     0x00000548
+#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2                     0x00000048
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0                      0x0000054c
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0                      0x0000004c
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1                      0x00000550
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1                      0x00000050
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2                      0x00000554
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2                      0x00000054
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3                      0x00000558
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3                      0x00000058
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4                      0x0000055c
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4                      0x0000005c
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5                      0x00000560
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5                      0x00000060
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6                      0x00000564
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6                      0x00000064
 
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7                      0x00000568
+#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7                      0x00000068
 
-#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL                                0x0000056c
+#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL                                0x0000006c
 
-#define REG_HDMI_8960_PHY_PLL_MISC0                            0x00000570
+#define REG_HDMI_8960_PHY_PLL_MISC0                            0x00000070
 
-#define REG_HDMI_8960_PHY_PLL_MISC1                            0x00000574
+#define REG_HDMI_8960_PHY_PLL_MISC1                            0x00000074
 
-#define REG_HDMI_8960_PHY_PLL_MISC2                            0x00000578
+#define REG_HDMI_8960_PHY_PLL_MISC2                            0x00000078
 
-#define REG_HDMI_8960_PHY_PLL_MISC3                            0x0000057c
+#define REG_HDMI_8960_PHY_PLL_MISC3                            0x0000007c
 
-#define REG_HDMI_8960_PHY_PLL_MISC4                            0x00000580
+#define REG_HDMI_8960_PHY_PLL_MISC4                            0x00000080
 
-#define REG_HDMI_8960_PHY_PLL_MISC5                            0x00000584
+#define REG_HDMI_8960_PHY_PLL_MISC5                            0x00000084
 
-#define REG_HDMI_8960_PHY_PLL_MISC6                            0x00000588
+#define REG_HDMI_8960_PHY_PLL_MISC6                            0x00000088
 
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0                       0x0000058c
+#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0                       0x0000008c
 
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1                       0x00000590
+#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1                       0x00000090
 
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2                       0x00000594
+#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2                       0x00000094
 
-#define REG_HDMI_8960_PHY_PLL_STATUS0                          0x00000598
+#define REG_HDMI_8960_PHY_PLL_STATUS0                          0x00000098
 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK                     0x00000001
 
-#define REG_HDMI_8960_PHY_PLL_STATUS1                          0x0000059c
+#define REG_HDMI_8960_PHY_PLL_STATUS1                          0x0000009c
 
 #define REG_HDMI_8x74_ANA_CFG0                                 0x00000000