default:
SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
sih->bustype));
- ASSERT(0);
return;
}
eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
if (coreidx >= sii->numcores)
return NULL;
- /*
- * If the user has provided an interrupt mask enabled function,
- * then assert interrupts are disabled before switching the core.
- */
- ASSERT((sii->intrsenabled_fn == NULL)
- || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
-
switch (sih->bustype) {
case SI_BUS:
/* map new one */
if (!sii->regs[coreidx]) {
sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->regs[coreidx]));
}
sii->curmap = regs = sii->regs[coreidx];
if (!sii->wrappers[coreidx]) {
sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->wrappers[coreidx]));
}
sii->curwrap = sii->wrappers[coreidx];
break;
break;
default:
- ASSERT(0);
regs = NULL;
break;
}
sii = SI_INFO(sih);
- ASSERT(GOODIDX(coreidx));
- ASSERT(regoff < SI_CORE_SIZE);
- ASSERT((val & ~mask) == 0);
-
if (coreidx >= SI_MAXCORES)
return 0;
if (!sii->regs[coreidx]) {
sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->regs[coreidx]));
}
r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
} else if (sih->bustype == PCI_BUS) {
r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
regoff);
}
- ASSERT(r != NULL);
/* mask and set */
if (mask || val) {
sii = SI_INFO(sih);
- ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
/* if core is already in reset, just return */
volatile u32 dummy;
sii = SI_INFO(sih);
- ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
/*
return;
}
- ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
- ASSERT((val & ~mask) == 0);
-
if (mask || val) {
w = ((R_REG(&ai->ioctrl) & ~mask) | val);
W_REG(&ai->ioctrl, w);
return 0;
}
- ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
- ASSERT((val & ~mask) == 0);
-
if (mask || val) {
w = ((R_REG(&ai->ioctrl) & ~mask) | val);
W_REG(&ai->ioctrl, w);
return 0;
}
- ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
- ASSERT((val & ~mask) == 0);
- ASSERT((mask & ~SISF_CORE_BITS) == 0);
-
if (mask || val) {
w = ((R_REG(&ai->iostatus) & ~mask) | val);
W_REG(&ai->iostatus, w);
int prec;
for (prec = 0; prec < pq->num_prec; prec++)
pktq_pflush(pq, prec, dir, fn, arg);
- if (fn == NULL)
- ASSERT(pq->len == 0);
}
#endif /* BRCM_FULLMAC */
{
int prec;
- ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
-
/* pq is variable size; only zero out what's requested */
memset(pq, 0,
offsetof(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));
return CHSPEC_CHANNEL(chspec);
} else {
/* we only support 40MHZ with sidebands */
- ASSERT(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_40);
/* chanspec channel holds the centre frequency, use that and the
* side band information to reconstruct the control channel number
*/
/* control chan is the upper 20 MHZ SB of the 40MHZ channel */
ctl_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec));
} else {
- ASSERT(CHSPEC_CTL_SB(chspec) ==
- WL_CHANSPEC_CTL_SB_LOWER);
/* control chan is the lower 20 MHZ SB of the 40MHZ channel */
ctl_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec));
}
di->msg_level = msg_level ? msg_level : &dma_msg_level;
- /* old chips w/o sb is no longer supported */
- ASSERT(sih != NULL);
-
di->dma64 = ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
- /* check arguments */
- ASSERT(ISPOWEROF2(ntxd));
- ASSERT(ISPOWEROF2(nrxd));
-
- if (nrxd == 0)
- ASSERT(dmaregsrx == NULL);
- if (ntxd == 0)
- ASSERT(dmaregstx == NULL);
-
/* init dma reg pointer */
- ASSERT(ntxd <= D64MAXDD);
- ASSERT(nrxd <= D64MAXDD);
di->d64txregs = (dma64regs_t *) dmaregstx;
di->d64rxregs = (dma64regs_t *) dmaregsrx;
di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
#else
if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
- ASSERT((PHYSADDRHI(pa) & PCI64ADDR_HIGH) == 0);
W_SM(&ddring[outidx].addrlow,
BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
} else {
/* address extension for 32-bit PCI */
u32 ae;
- ASSERT(di->addrext);
ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
- ASSERT(PHYSADDRHI(pa) == 0);
ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
W_SM(&ddring[outidx].addrlow,
DMA_TRACE(("%s: dma_detach\n", di->name));
- /* shouldn't be here if descriptors are unreclaimed */
- ASSERT(di->txin == di->txout);
- ASSERT(di->rxin == di->rxout);
-
/* free dma descriptor rings */
if (di->txd64)
pci_free_consistent(di->pbus, di->txdalloc,
if (!_dma64_addrext(di->d64txregs)) {
DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
"AE set\n", di->name));
- ASSERT(0);
}
return true;
} else if (di->d64rxregs != NULL) {
if (!_dma64_addrext(di->d64rxregs)) {
DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
"AE set\n", di->name));
- ASSERT(0);
}
return true;
}
} else {
/* DMA64 32bits address extension */
u32 ae;
- ASSERT(di->addrext);
- ASSERT(PHYSADDRHI(pa) == 0);
/* shift the high bit(s) from pa to ae */
ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
#ifdef BCMDBG
if (resid > 0) {
uint cur;
- ASSERT(p == NULL);
cur =
B2I(((R_REG(&di->d64rxregs->status0) &
D64_RS0_CD_MASK) -
pa = pci_map_single(di->pbus, p->data,
di->rxbufsize, PCI_DMA_FROMDEVICE);
- ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4));
-
/* save the free packet pointer */
- ASSERT(di->rxp[rxout] == NULL);
di->rxp[rxout] = p;
/* reset flags for each descriptor */
return 0;
}
- ASSERT((flags & ~mask) == 0);
-
dmactrlflags &= ~mask;
dmactrlflags |= flags;
{
if (!strcmp(name, "&txavail"))
return (unsigned long)&(di->hnddma.txavail);
- else {
- ASSERT(0);
- }
return 0;
}
u8 dma_align_sizetobits(uint size)
{
u8 bitpos = 0;
- ASSERT(size);
- ASSERT(!(size & (size - 1)));
while (size >>= 1) {
bitpos++;
}
di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
PHYSADDRLOSET(di->txdpa,
PHYSADDRLO(di->txdpaorig) + di->txdalign);
- /* Make sure that alignment didn't overflow */
- ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
-
PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
di->txdalloc = alloced;
- ASSERT(IS_ALIGNED((unsigned long)di->txd64, align));
} else {
va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
&alloced, &di->rxdpaorig);
di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
PHYSADDRLOSET(di->rxdpa,
PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
- /* Make sure that alignment didn't overflow */
- ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
-
PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
di->rxdalloc = alloced;
- ASSERT(IS_ALIGNED((unsigned long)di->rxd64, align));
}
return true;
flags |= D64_CTRL1_EOT;
dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
- ASSERT(di->txp[txout] == NULL);
/* save the buffer pointer - used by dma_getpos */
di->txp[txout] = buf;
pa = map->segs[j - 1].addr;
}
dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
- ASSERT(di->txp[txout] == NULL);
txout = NEXTTXD(txout);
}
void *rxp;
dmaaddr_t pa;
- /* if forcing, dma engine must be disabled */
- ASSERT(!forceall || !dma64_rxenabled(di));
-
i = di->rxin;
/* return if no packets posted */
/* get the packet pointer that corresponds to the rx descriptor */
rxp = di->rxp[i];
- ASSERT(rxp);
di->rxp[i] = NULL;
PHYSADDRLOSET(pa,
u32 w;
u16 first, last;
- ASSERT(dma64_txsuspendedidle(di));
-
nactive = _dma_txactive(di);
ad = (u16) (B2I
((((R_REG(&di->d64txregs->status1) &
- di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
rot = TXD(ad - di->txin);
- ASSERT(rot < di->ntxd);
-
/* full-ring case is a lot harder - don't worry about this */
if (rot >= (di->ntxd - nactive)) {
DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
/* move the corresponding txp[] entry */
- ASSERT(di->txp[new] == NULL);
di->txp[new] = di->txp[old];
/* Move the map */
(sih->buscoretype == PCIE_CORE_ID)))
return DMADDRWIDTH_64;
}
- ASSERT(0); /* DMA hardware not supported by this driver*/
+ /* DMA hardware not supported by this driver*/
return DMADDRWIDTH_64;
}
chipcregs_t *cc;
uint origidx;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
W_REG(&cc->regcontrol_addr, 0x01);
W_REG(&cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
u8 addr = 0;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
switch (sih->chip) {
case BCM4336_CHIP_ID:
switch (ldo) {
mask = 0xf;
break;
default:
- ASSERT(false);
return;
}
break;
mask = 0x1f;
break;
default:
- ASSERT(false);
break;
}
break;
default:
- ASSERT(false);
return;
}
chn[0] = 0; /* to suppress compile error */
#endif
- ASSERT(sih->cccaps & CC_CAP_PMU);
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM43224_CHIP_ID:
uint origidx;
u32 oldpmucontrol;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
oldpmucontrol = R_REG(&cc->pmucontrol);
if (force)
char name[8], *val;
uint i, rsrcs;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM4329_CHIP_ID:
/* Program up/down timers */
while (pmu_res_updown_table_sz--) {
- ASSERT(pmu_res_updown_table != NULL);
PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
pmu_res_updown_table[pmu_res_updown_table_sz].resnum,
pmu_res_updown_table[pmu_res_updown_table_sz].updown));
/* Program resource dependencies table */
while (pmu_res_depend_table_sz--) {
- ASSERT(pmu_res_depend_table != NULL);
if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
&& !(pmu_res_depend_table[pmu_res_depend_table_sz].
filter) (sih))
[pmu_res_depend_table_sz].depend_mask);
break;
default:
- ASSERT(0);
break;
}
}
bcm_chipname(sih->chip, chn, 8)));
break;
}
- ASSERT(0);
return NULL;
}
bcm_chipname(sih->chip, chn, 8)));
break;
}
- ASSERT(0);
return NULL;
}
bcm_chipname(sih->chip, chn, 8)));
break;
}
- ASSERT(0);
return 0;
}
/* Could not find it so assign a default value */
if (xt == NULL || xt->fref == 0)
xt = si_pmu1_xtaldef0(sih);
- ASSERT(xt != NULL && xt->fref != 0);
-
return xt->fref * 1000;
}
PMURES_BIT(RES4329_HT_AVAIL)));
SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
if (xt->fref == 38400)
tmp = 0x200024C0;
udelay(100);
SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
tmp = 0x200005c0;
W_REG(&cc->pllcontrol_data, tmp);
udelay(100);
SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
break;
case BCM4330_CHIP_ID:
udelay(100);
SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
break;
default:
- ASSERT(0);
+ break;
}
PMU_MSG(("Done masking\n"));
char chn[8];
#endif
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM4329_CHIP_ID:
char chn[8];
#endif
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM43224_CHIP_ID:
char chn[8];
#endif
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM43224_CHIP_ID:
uint origidx;
u32 clock;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
if ((sih->pmurev >= 5) &&
!((sih->chip == BCM4329_CHIP_ID) ||
(sih->chip == BCM4319_CHIP_ID) ||
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_CPU);
uint origidx;
u32 clock;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
if ((sih->pmurev >= 5) &&
!((sih->chip == BCM4329_CHIP_ID) ||
(sih->chip == BCM4319_CHIP_ID) ||
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_MEM);
u32 start, end, delta;
u32 origidx = si_coreidx(sih);
chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
start = R_REG(&cc->pmutimer);
mdelay(ILP_CALC_DUR);
end = R_REG(&cc->pmutimer);
chipcregs_t *cc;
uint origidx;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
if (sih->pmurev == 1)
AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
uint origidx;
u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Don't do anything if OTP is disabled */
if (si_is_otp_disabled(sih)) {
PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM4329_CHIP_ID:
OR_REG(&cc->min_res_mask, (rsrcs | deps));
SPINWAIT(!(R_REG(&cc->res_state) & rsrcs),
PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG(&cc->res_state) & rsrcs);
} else {
PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n",
rsrcs | deps));
SPINWAIT((((otps = R_REG(&cc->otpstatus)) & OTPS_READY) !=
(on ? OTPS_READY : 0)), 100);
- ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0));
if ((otps & OTPS_READY) != (on ? OTPS_READY : 0))
PMU_MSG(("OTP ready bit not %s after wait\n",
(on ? "ON" : "OFF")));
chipcregs_t *cc;
uint origidx;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM4329_CHIP_ID:{
/* Wait for completion */
SPINWAIT(0 == (R_REG(&cc->chipstatus) & 0x08),
10 * 1000 * 1000);
- ASSERT(R_REG(&cc->chipstatus) & 0x08);
/* Drop the LSB to convert from 5 bit code to 4 bit code */
rcal_code =
/* Remember original core before switch to chipc */
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
&intr_val);
- ASSERT(cc != NULL);
/* force the HT off */
if (sih->chip == BCM4336_CHIP_ID) {
/* wait for the ht to really go away */
SPINWAIT(((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
10000);
- ASSERT((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0);
}
/* update the pll changes */
/* Remember original core before switch to chipc */
idx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
switch (sih->chip) {
case BCM4329_CHIP_ID:
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
/* Return to original core */
si_setcoreidx(sih, origidx);
{
uint origidx;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Gate off SPROM clock and chip select signals */
si_pmu_sprom_enable(sih, false);
/* initialize PMU switch/regulators */
void si_pmu_swreg_init(si_t *sih)
{
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
switch (sih->chip) {
case BCM4336_CHIP_ID:
/* Reduce CLDO PWM output voltage to 1.2V */
void si_pmu_radio_enable(si_t *sih, bool enable)
{
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
switch (sih->chip) {
case BCM4319_CHIP_ID:
if (enable)
chipcregs_t *cc;
uint origidx;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
if (delay)
SPINWAIT(((R_REG(&cc->pmustatus) & clk) != clk), delay);
if (sih->pmurev < 10)
return 0;
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
/* Remember original core before switch to chipc */
origidx = si_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
u32 ilp_ctr, alp_hz;
{
pcicore_info_t *pi;
- ASSERT(sih->bustype == PCI_BUS);
-
/* alloc pcicore_info_t */
pi = kzalloc(sizeof(pcicore_info_t), GFP_ATOMIC);
if (pi == NULL) {
pi->regs.pcieregs = (sbpcieregs_t *) regs;
cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
NULL, NULL);
- ASSERT(cap_ptr);
pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
} else
pi->regs.pciregs = (struct sbpciregs *) regs;
{
uint retval = 0xFFFFFFFF;
- ASSERT(pcieregs != NULL);
-
switch (addrtype) {
case PCIE_CONFIGREGS:
W_REG((&pcieregs->configaddr), offset);
retval = R_REG(&(pcieregs->pcieinddata));
break;
default:
- ASSERT(0);
break;
}
pcie_writereg(sbpcieregs_t *pcieregs, uint addrtype,
uint offset, uint val)
{
- ASSERT(pcieregs != NULL);
-
switch (addrtype) {
case PCIE_CONFIGREGS:
W_REG((&pcieregs->configaddr), offset);
W_REG((&pcieregs->pcieinddata), val);
break;
default:
- ASSERT(0);
break;
}
return 0;
static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
{
si_t *sih = pi->sih;
- ASSERT(PCIE_PUB(sih));
switch (state) {
case SI_DOATTACH:
}
break;
default:
- ASSERT(0);
break;
}
}
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
u16 *reg16;
- ASSERT(pi->sih->buscorerev == 7);
-
/* turn off serdes PLL down */
si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
u16 u16offset;
s32 s32log;
- /* Logerithm of negative values is undefined.
- * assert N is greater than 0.
- */
- /* ASSERT(N > 0); */
-
/* normalize the N. */
s16norm = qm_norm32(N);
N = N << s16norm;
uint pciidx, pcieidx, pcirev, pcierev;
cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
- ASSERT(cc);
/* get chipcommon rev */
sii->pub.ccrev = (int)si_corerev(&sii->pub);
if (sii->pub.boardtype == 0) {
SI_ERROR(("si_doattach: unknown board type\n"));
- ASSERT(sii->pub.boardtype);
}
sii->pub.boardflags = getintvar(pvars, "boardflags");
chipcregs_t *cc;
uint origidx;
- ASSERT(GOODREGS(regs));
-
memset((unsigned char *) sii, 0, sizeof(si_info_t));
savewin = 0;
char *pvars = NULL;
uint origidx;
- ASSERT(GOODREGS(regs));
-
memset((unsigned char *) sii, 0, sizeof(si_info_t));
savewin = 0;
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
if (PCIE(sii)) {
- ASSERT(sii->pch != NULL);
pcicore_attach(sii->pch, pvars, SI_DOATTACH);
}
if (sih->socitype == SOCI_AI)
return ai_flag(sih);
else {
- ASSERT(0);
return 0;
}
}
{
if (sih->socitype == SOCI_AI)
ai_setint(sih, siflag);
- else
- ASSERT(0);
}
#ifndef BCMSDIO
{
if (sih->socitype == SOCI_AI)
return ai_corerev(sih);
- else {
- ASSERT(0);
- return 0;
- }
+ return 0;
}
#endif
#ifdef BCMSDIO
return sb_setcoreidx(sih, idx);
#else
- ASSERT(0);
return NULL;
#endif
}
if (sih->socitype == SOCI_AI)
return ai_setcoreidx(sih, coreidx);
else {
- ASSERT(0);
return NULL;
}
}
INTR_OFF(sii, *intr_val);
*origidx = sii->curidx;
cc = si_setcore(sih, coreid, 0);
- ASSERT(cc != NULL);
return cc;
}
if (sih->socitype == SOCI_AI)
return ai_core_cflags(sih, mask, val);
else {
- ASSERT(0);
return 0;
}
}
if (sih->socitype == SOCI_AI)
return ai_core_sflags(sih, mask, val);
else {
- ASSERT(0);
return 0;
}
}
#ifdef BCMSDIO
return sb_iscoreup(sih);
#else
- ASSERT(0);
return false;
#endif
}
#ifdef BCMSDIO
return sb_corereg(sih, coreidx, regoff, mask, val);
#else
- ASSERT(0);
return 0;
#endif
}
chipcregs_t *cc;
u32 val;
- ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
-
if (sii->pub.ccrev < 6) {
if (sii->pub.bustype == PCI_BUS) {
pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
u32 slowclk;
uint div;
- ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
-
- /* shouldn't be here unless we've established the chip has dynamic clk control */
- ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL);
-
slowclk = si_slowclk_src(sii);
if (sii->pub.ccrev < 6) {
if (slowclk == SCC_SS_PCI)
else if (slowclk == SCC_SS_PCI)
return max_freq ? (PCIMAXFREQ / div)
: (PCIMINFREQ / div);
- else
- ASSERT(0);
} else {
/* Chipc rev 10 is InstaClock */
div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
if (cc == NULL)
return;
}
- ASSERT(cc != NULL);
/* set all Instaclk chip ILP to 1 MHz */
if (sih->ccrev >= 10)
if (cc == NULL)
goto done;
}
- ASSERT(cc != NULL);
slowminfreq = si_slowclk_freq(sii, false, cc);
fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
if (sii->pub.ccrev < 6)
return false;
- /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
- ASSERT(sii->pub.ccrev != 10);
-
if (!fast) {
INTR_OFF(sii, intr_val);
origidx = sii->curidx;
if (cc == NULL)
goto done;
}
- ASSERT(cc != NULL);
if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
goto done;
u32 htavail = CCS_HTAVAIL;
SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
== 0), PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG(&cc->clk_ctl_st) & htavail);
} else {
udelay(PLL_DELAY);
}
break;
default:
- ASSERT(0);
+ break;
}
done:
{
int slen;
- ASSERT(path != NULL);
- ASSERT(size >= SI_DEVPATH_BUFSZ);
-
if (!path || size <= 0)
return -1;
slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));
break;
case PCI_BUS:
- ASSERT((SI_INFO(sih))->pbus != NULL);
slen = snprintf(path, (size_t) size, "pci/%u/%u/",
((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
PCI_SLOT(
#endif
default:
slen = -1;
- ASSERT(0);
break;
}
/* get the current core index */
idx = sii->curidx;
- ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0));
/* switch to sdio core */
sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0);
if (!sdpregs)
sdpregs =
(sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0);
- ASSERT(sdpregs);
SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
if (sii->pub.bustype != PCI_BUS)
return;
- ASSERT(PCI(sii) || PCIE(sii));
- ASSERT(sii->pub.buscoreidx != BADIDX);
-
if (PCI(sii)) {
/* get current core index */
idx = sii->curidx;
si_info_t *sii = SI_INFO(sih);
- ASSERT(sii->pub.bustype == PCI_BUS);
-
/* Fixup PI in SROM shadow area to enable the correct PCI core access */
/* save the current index */
origidx = si_coreidx(&sii->pub);
pcieregs =
(sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0);
regs = pcieregs;
- ASSERT(pcieregs != NULL);
reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
} else if (sii->pub.buscoretype == PCI_CORE_ID) {
pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
regs = pciregs;
- ASSERT(pciregs != NULL);
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
}
pciidx = si_coreidx(&sii->pub);
uint banksize, bankinfo;
uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
- ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
-
W_REG(®s->bankidx, bankidx);
bankinfo = R_REG(®s->bankinfo);
banksize =
switch (sih->bustype) {
case PCI_BUS:
- ASSERT(sii->pbus != NULL);
pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
return true;
projects / openwrt / staging / blogic.git / commitdiff