drm/i915/dp: cache source rates at init
authorJani Nikula <jani.nikula@intel.com>
Tue, 28 Mar 2017 14:59:04 +0000 (17:59 +0300)
committerJani Nikula <jani.nikula@intel.com>
Thu, 6 Apr 2017 11:33:55 +0000 (14:33 +0300)
We need the source rates array so often that it makes sense to set it
once at init. This reduces function calls when we need the rates, making
the code easier to follow.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/aa998882d2b824f671272c60e9d26621ab9d2d17.1490712890.git.jani.nikula@intel.com
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h

index 9fc066dda4e0cdc70117de81d7cb0b744bde6bef..e9bd75ff3904a8e4fae13c254a9474c96b9bd654 100644 (file)
@@ -218,21 +218,25 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
        return (intel_dp->max_sink_link_bw >> 3) + 1;
 }
 
-static int
-intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
+static void
+intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+       const int *source_rates;
        int size;
 
+       /* This should only be done once */
+       WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
+
        if (IS_GEN9_LP(dev_priv)) {
-               *source_rates = bxt_rates;
+               source_rates = bxt_rates;
                size = ARRAY_SIZE(bxt_rates);
        } else if (IS_GEN9_BC(dev_priv)) {
-               *source_rates = skl_rates;
+               source_rates = skl_rates;
                size = ARRAY_SIZE(skl_rates);
        } else {
-               *source_rates = default_rates;
+               source_rates = default_rates;
                size = ARRAY_SIZE(default_rates);
        }
 
@@ -240,7 +244,8 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
        if (!intel_dp_source_supports_hbr2(intel_dp))
                size--;
 
-       return size;
+       intel_dp->source_rates = source_rates;
+       intel_dp->num_source_rates = size;
 }
 
 static int intersect_rates(const int *source_rates, int source_len,
@@ -281,13 +286,13 @@ static int intel_dp_rate_index(const int *rates, int len, int rate)
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
                                 int *common_rates)
 {
-       const int *source_rates, *sink_rates;
-       int source_len, sink_len;
+       const int *sink_rates;
+       int sink_len;
 
        sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
-       source_len = intel_dp_source_rates(intel_dp, &source_rates);
 
-       return intersect_rates(source_rates, source_len,
+       return intersect_rates(intel_dp->source_rates,
+                              intel_dp->num_source_rates,
                               sink_rates, sink_len,
                               common_rates);
 }
@@ -1493,16 +1498,16 @@ static void snprintf_int_array(char *str, size_t len,
 
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
-       const int *source_rates, *sink_rates;
-       int source_len, sink_len, common_len;
+       const int *sink_rates;
+       int sink_len, common_len;
        int common_rates[DP_MAX_SUPPORTED_RATES];
        char str[128]; /* FIXME: too big for stack? */
 
        if ((drm_debug & DRM_UT_KMS) == 0)
                return;
 
-       source_len = intel_dp_source_rates(intel_dp, &source_rates);
-       snprintf_int_array(str, sizeof(str), source_rates, source_len);
+       snprintf_int_array(str, sizeof(str),
+                          intel_dp->source_rates, intel_dp->num_source_rates);
        DRM_DEBUG_KMS("source rates: %s\n", str);
 
        sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
@@ -5943,6 +5948,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
                 intel_dig_port->max_lanes, port_name(port)))
                return false;
 
+       intel_dp_set_source_rates(intel_dp);
+
        intel_dp->reset_link_params = true;
        intel_dp->pps_pipe = INVALID_PIPE;
        intel_dp->active_pipe = INVALID_PIPE;
index 313fad059bfa0b7608b952122a404134733311dd..c3382eb580b5bcdf4a9863a4f5241549380b2df9 100644 (file)
@@ -949,6 +949,9 @@ struct intel_dp {
        uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
        uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
        uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+       /* source rates */
+       int num_source_rates;
+       const int *source_rates;
        /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
        uint8_t num_sink_rates;
        int sink_rates[DP_MAX_SUPPORTED_RATES];