drm/amdgpu: move firmware definitions into amdgpu_ucode header
authorHuang Rui <ray.huang@amd.com>
Thu, 2 Aug 2018 09:47:15 +0000 (17:47 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:09:55 +0000 (11:09 -0500)
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

index 159854eaf55364aa05ee4d537478dee06919bab9..d39053d06b277929b2816d79fae0ffff6e5029d9 100644 (file)
@@ -714,33 +714,6 @@ struct amdgpu_wb {
 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
 
-/*
- * Firmware
- */
-enum amdgpu_firmware_load_type {
-       AMDGPU_FW_LOAD_DIRECT = 0,
-       AMDGPU_FW_LOAD_SMU,
-       AMDGPU_FW_LOAD_PSP,
-};
-
-struct amdgpu_firmware {
-       struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
-       enum amdgpu_firmware_load_type load_type;
-       struct amdgpu_bo *fw_buf;
-       unsigned int fw_size;
-       unsigned int max_ucodes;
-       /* firmwares are loaded by psp instead of smu from vega10 */
-       const struct amdgpu_psp_funcs *funcs;
-       struct amdgpu_bo *rbuf;
-       struct mutex mutex;
-
-       /* gpu info firmware data pointer */
-       const struct firmware *gpu_info_fw;
-
-       void *fw_buf_ptr;
-       uint64_t fw_buf_mc;
-};
-
 /*
  * Benchmarking
  */
index bdc472b6e64136ca5d0211429aee15cff6de152d..a1edc70da979cd55172ebbd5b21d8856965a07f8 100644 (file)
@@ -205,6 +205,12 @@ enum AMDGPU_UCODE_STATUS {
        AMDGPU_UCODE_STATUS_LOADED,
 };
 
+enum amdgpu_firmware_load_type {
+       AMDGPU_FW_LOAD_DIRECT = 0,
+       AMDGPU_FW_LOAD_SMU,
+       AMDGPU_FW_LOAD_PSP,
+};
+
 /* conform to smu_ucode_xfer_cz.h */
 #define AMDGPU_SDMA0_UCODE_LOADED      0x00000001
 #define AMDGPU_SDMA1_UCODE_LOADED      0x00000002
@@ -232,6 +238,24 @@ struct amdgpu_firmware_info {
        uint32_t tmr_mc_addr_hi;
 };
 
+struct amdgpu_firmware {
+       struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
+       enum amdgpu_firmware_load_type load_type;
+       struct amdgpu_bo *fw_buf;
+       unsigned int fw_size;
+       unsigned int max_ucodes;
+       /* firmwares are loaded by psp instead of smu from vega10 */
+       const struct amdgpu_psp_funcs *funcs;
+       struct amdgpu_bo *rbuf;
+       struct mutex mutex;
+
+       /* gpu info firmware data pointer */
+       const struct firmware *gpu_info_fw;
+
+       void *fw_buf_ptr;
+       uint64_t fw_buf_mc;
+};
+
 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);