drm/i915: fix tiling on IGDNG

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a2d527b22ec4f7ba837d9787f11585cf141cf844..e774a4a1a503514000f970afefeb91ef0af9c9d2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
        uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
        bool need_disable;
 
-       if (!IS_I9XX(dev)) {
+       if (IS_IGDNG(dev)) {
+               /* On IGDNG whatever DRAM config, GPU always do
+                * same swizzling setup.
+                */
+               swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+               swizzle_y = I915_BIT_6_SWIZZLE_9;
+       } else if (!IS_I9XX(dev)) {
                /* As far as we know, the 865 doesn't have these bit 6
                 * swizzling issues.
                 */
@@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                }
        }
 
-       /* FIXME: check with memory config on IGDNG */
-       if (IS_IGDNG(dev)) {
-               DRM_ERROR("disable tiling on IGDNG...\n");
-               swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-               swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-       }
-
        dev_priv->mm.bit_6_swizzle_x = swizzle_x;
        dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 884757ce5b67d4c5095a47197aca9ce74e44a225..e38cd21161c8f21f8f0f4650d1ce68f3d5276b12 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1864,6 +1864,7 @@
 #define   DISPPLANE_NO_LINE_DOUBLE             0
 #define   DISPPLANE_STEREO_POLARITY_FIRST      0
 #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
+#define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* IGDNG */
 #define   DISPPLANE_TILED                      (1<<10)
 #define DSPAADDR               0x70184
 #define DSPASTRIDE             0x70188
@@ -2044,6 +2045,9 @@
 #define GTIIR   0x44018
 #define GTIER   0x4401c
 
+#define DISP_ARB_CTL   0x45000
+#define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
+
 /* PCH */
 
 /* south display engine interrupt */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 867a969980eca1cb6af4cbdf2d923b58103426fe..d7c7fa489872511426888ef019ff2ae1b09c1e40 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1064,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                        dspcntr &= ~DISPPLANE_TILED;
        }
 
+       if (IS_IGDNG(dev))
+               /* must disable */
+               dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
        I915_WRITE(dspcntr_reg, dspcntr);
 
        Start = obj_priv->gtt_offset;
@@ -2719,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
        intel_wait_for_vblank(dev);
 
+       if (IS_IGDNG(dev)) {
+               /* enable address swizzle for tiling buffer */
+               temp = I915_READ(DISP_ARB_CTL);
+               I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+       }
+
        I915_WRITE(dspcntr_reg, dspcntr);
 
        /* Flush the plane changes */