DDR_CONFIG_easy50812_DDR166M_ramboot:=easy50812
#Arcadyan
-Package/uboot-lantiq-arv4518PW=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
+Package/uboot-lantiq-arv3527P_flash=$(call Package/uboot-lantiq-template,arv3527P_flash,NOR)
+Package/uboot-lantiq-arv3527P_ramboot=$(call Package/uboot-lantiq-template,arv3527P_ramboot,RAM)
+Package/uboot-lantiq-arv3527P_brnboot=$(call Package/uboot-lantiq-template,arv3527P_brnboot,BRN)
+Package/uboot-lantiq-arv4518PW_flash=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
Package/uboot-lantiq-arv4518PW_ramboot=$(call Package/uboot-lantiq-template,arv4518PW_ramboot,RAM)
Package/uboot-lantiq-arv4518PW_brnboot=$(call Package/uboot-lantiq-template,arv4518PW_brnboot,BRN)
-Package/uboot-lantiq-arv452CPW=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
+Package/uboot-lantiq-arv4520PW_flash=$(call Package/uboot-lantiq-template,arv4520PW_flash,NOR)
+Package/uboot-lantiq-arv4520PW_ramboot=$(call Package/uboot-lantiq-template,arv4520PW_ramboot,RAM)
+Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4520PW_brnboot,BRN)
+Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
+Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
+Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
+Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
-Package/uboot-lantiq-arv752DPW=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
+Package/uboot-lantiq-arv752DPW_flash=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
Package/uboot-lantiq-arv752DPW_ramboot=$(call Package/uboot-lantiq-template,arv752DPW_ramboot,RAM)
Package/uboot-lantiq-arv752DPW_brnboot=$(call Package/uboot-lantiq-template,arv752DPW_brnboot,BRN)
-Package/uboot-lantiq-arv752DPW22=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
+Package/uboot-lantiq-arv752DPW22_flash=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
Package/uboot-lantiq-arv752DPW22_ramboot=$(call Package/uboot-lantiq-template,arv752DPW22_ramboot,RAM)
Package/uboot-lantiq-arv752DPW22_brnboot=$(call Package/uboot-lantiq-template,arv752DPW22_brnboot,BRN)
-DDR_CONFIG_arv4518_ramboot:=arcadyan_psc166
-DDR_CONFIG_arv452C_ramboot:=arcadyan_psc166
-DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166
-DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166
+DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
+DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
+DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
+DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
+DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
+DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
+DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
define Build/Prepare
$(PKG_UNPACK)
define Package/uboot-lantiq-$(BUILD_VARIANT)/install
mkdir -p $(1)
+ifneq ($(findstring flash,$(BUILD_VARIANT)),)
+ dd \
+ if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
+ of=$(1)/u-boot-bootstrap.bin \
+ bs=64k conv=sync
+else
dd \
if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
of=$(1)/u-boot.bin \
bs=64k conv=sync
+endif
ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
perl ./gct \
$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4518PW))
+#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_flash))
+#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_brnboot))
+#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_ramboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv452CPW))
+$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_flash))
+$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_brnboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
+$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW))
+$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22))
+$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_ramboot))
+++ /dev/null
- 0xbf800060 0x7
- 0xbf800010 0x0
- 0xbf800020 0x0
- 0xbf800200 0x02
- 0xbf800210 0x0
-
-;REG32(MC_DC0) = 0x00001B1B;
- 0xbf801000 0x1b1b
-;REG32(MC_DC1) = 0x00000000;
- 0xbf801010 0x0
-;REG32(MC_DC2) = 0x00000000;
- 0xbf801020 0x0
-;REG32(MC_DC3) = 0x00000000;
- 0xbf801030 0x0
-;REG32(MC_DC4) = 0x00000000;
- 0xbf801040 0x0
-;REG32(MC_DC5) = 0x00000200;
- 0xbf801050 0x200
-;REG32(MC_DC6) = 0x00000306;
-; 0xbf801060 0x0306
- 0xbf801060 0x0605
-;REG32(MC_DC7) = 0x00000303;
-; 0xbf801070 0x302
-; 0xbf801070 0x0203
- 0xbf801070 0x0303
-;REG32(MC_DC8) = 0x00000102;
- 0xbf801080 0x102
-;REG32(MC_DC9) = 0x0000070A;
- 0xbf801090 0x70a
-; 0xbf801090 0x608
-;REG32(MC_DC10) = 0x00000203;
- 0xbf8010a0 0x203
-;REG32(MC_DC11) = 0x00000C02;
- 0xbf8010b0 0xc02
-; 0xbf8010b0 0x0a02
-;REG32(MC_DC12) = 0x000001C8;
- 0xbf8010c0 0x1c8
-;REG32(MC_DC13) = 0x00000001;
- 0xbf8010d0 0x1
-;REG32(MC_DC14) = 0x00000000;
- 0xbf8010e0 0x0
-;REG32(MC_DC15) = 0x00000F5F;
-; 0xbf8010f0 0xf5f
-; 0xbf8010f0 0xf3c
- 0xbf8010f0 0x130
-;REG32(MC_DC16) = 0x0000C800;
- 0xbf801100 0xc800
-;REG32(MC_DC17) = 0x0000000D;
-; 0xbf801110 0xd
- 0xbf801110 0xd
-;REG32(MC_DC18) = 0x00000300;
-; 0xbf801120 0x300
- 0xbf801120 0x301
-;REG32(MC_DC19) = 0x00000300;
-; 0xbf801130 0x300
- 0xbf801130 0x200
-;REG32(MC_DC20) = 0x00000A04;
-; 0xbf801140 0xa04
- 0xbf801140 0xa03
-;REG32(MC_DC21) = 0x00001c00;
-; 0xbf801150 0xd00
-; 0xbf801150 0x1f00
- 0xbf801150 0x1b00
-;REG32(MC_DC22) = 0x00001E1E;
-; 0xbf801160 0xd0d
-; 0xbf801160 0x1f1f
- 0xbf801160 0x1b1b
-;REG32(MC_DC23) = 0x00000000;
- 0xbf801170 0x0
-;//Disable ECC
-;REG32(MC_DC24) = 0x0000007F;
-; 0xbf801180 0x7f
-; 0xbf801180 0x062
-; 0xbf801180 0x37f
- 0xbf801180 0x59
-;REG32(MC_DC25) = 0x00000000;
- 0xbf801190 0x0
-;REG32(MC_DC26) = 0x00000000;
- 0xbf8011a0 0x0
-;REG32(MC_DC27) = 0x00000000;
- 0xbf8011b0 0x0
-;REG32(MC_DC28) = 0x00000A24;
-; 0xbf8011c0 0xa24
- 0xbf8011c0 0x510
-;REG32(MC_DC29) = 0x00002D89;
-; 0xbf8011d0 0x2d89
-; 0xbf8011d0 0x2d92
- 0xbf8011d0 0x4e20
-;REG32(MC_DC30) = 0x00000022;
-; 0xbf8011e0 0x8300
- 0xbf8011e0 0x8235
-;REG32(MC_DC31) = 0x00000000;
- 0xbf8011f0 0x0
-;REG32(MC_DC32) = 0x00000000;
- 0xbf801200 0x0
-;REG32(MC_DC33) = 0x00000000;
- 0xbf801210 0x0
-;REG32(MC_DC34) = 0x00000000;
- 0xbf801220 0x0
-;REG32(MC_DC35) = 0x00000000;
- 0xbf801230 0x0
-;REG32(MC_DC36) = 0x00000000;
- 0xbf801240 0x0
-;REG32(MC_DC37) = 0x00000000;
- 0xbf801250 0x0
-;REG32(MC_DC38) = 0x00000000;
- 0xbf801260 0x0
-;REG32(MC_DC39) = 0x00000000;
- 0xbf801270 0x0
-;REG32(MC_DC40) = 0x00000000;
- 0xbf801280 0x0
-;REG32(MC_DC41) = 0x00000000;
- 0xbf801290 0x0
-;REG32(MC_DC42) = 0x00000000;
- 0xbf8012a0 0x0
-;REG32(MC_DC43) = 0x00000000;
- 0xbf8012b0 0x0
-;REG32(MC_DC44) = 0x00000000;
- 0xbf8012c0 0x0
-;REG32(MC_DC45) = 0x00000600;
- 0xbf8012d0 0x500
-;REG32(MC_DC46) = 0x00000000;
- 0xbf8012e0 0x0
-
- 0xbf800060 0x05
- 0xbf801030 0x100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--- /dev/null
+ 0xbf800060 0x7
+ 0xbf800010 0x0
+ 0xbf800020 0x0
+ 0xbf800200 0x02
+ 0xbf800210 0x0
+
+ 0xbf801000 0x1b1b
+ 0xbf801010 0x0
+ 0xbf801020 0x0
+ 0xbf801030 0x0
+ 0xbf801040 0x0
+ 0xbf801050 0x200
+ 0xbf801060 0x605
+ 0xbf801070 0x0303
+ 0xbf801080 0x102
+ 0xbf801090 0x70a
+ 0xbf8010a0 0x203
+ 0xbf8010b0 0xc02
+ 0xbf8010c0 0x1c8
+ 0xbf8010d0 0x1
+ 0xbf8010e0 0x0
+ 0xbf8010f0 0x120
+ 0xbf801100 0xc800
+ 0xbf801110 0xd
+ 0xbf801120 0x301
+ 0xbf801130 0x200
+ 0xbf801140 0xa04
+ 0xbf801150 0x1700
+ 0xbf801160 0x1717
+ 0xbf801170 0x0
+ 0xbf801180 0x52
+ 0xbf801190 0x0
+ 0xbf8011a0 0x0
+ 0xbf8011b0 0x0
+ 0xbf8011c0 0x510
+ 0xbf8011d0 0x4e20
+ 0xbf8011e0 0x8235
+ 0xbf8011f0 0x0
+ 0xbf801200 0x0
+ 0xbf801210 0x0
+ 0xbf801220 0x0
+ 0xbf801230 0x0
+ 0xbf801240 0x0
+ 0xbf801250 0x0
+ 0xbf801260 0x0
+ 0xbf801270 0x0
+ 0xbf801280 0x0
+ 0xbf801290 0x0
+ 0xbf8012a0 0x0
+ 0xbf8012b0 0x0
+ 0xbf8012c0 0x0
+ 0xbf8012d0 0x500
+ 0xbf8012e0 0x0
+
+ 0xbf800060 0x05
+ 0xbf801030 0x100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+ 0xbf800060 0x7
+ 0xbf800010 0x0
+ 0xbf800020 0x0
+ 0xbf800200 0x02
+ 0xbf800210 0x0
+
+;REG32(MC_DC0) = 0x00001B1B;
+ 0xbf801000 0x1b1b
+;REG32(MC_DC1) = 0x00000000;
+ 0xbf801010 0x0
+;REG32(MC_DC2) = 0x00000000;
+ 0xbf801020 0x0
+;REG32(MC_DC3) = 0x00000000;
+ 0xbf801030 0x0
+;REG32(MC_DC4) = 0x00000000;
+ 0xbf801040 0x0
+;REG32(MC_DC5) = 0x00000200;
+ 0xbf801050 0x200
+;REG32(MC_DC6) = 0x00000306;
+; 0xbf801060 0x0306
+ 0xbf801060 0x0605
+;REG32(MC_DC7) = 0x00000303;
+; 0xbf801070 0x302
+; 0xbf801070 0x0203
+ 0xbf801070 0x0303
+;REG32(MC_DC8) = 0x00000102;
+ 0xbf801080 0x102
+;REG32(MC_DC9) = 0x0000070A;
+ 0xbf801090 0x70a
+; 0xbf801090 0x608
+;REG32(MC_DC10) = 0x00000203;
+ 0xbf8010a0 0x203
+;REG32(MC_DC11) = 0x00000C02;
+ 0xbf8010b0 0xc02
+; 0xbf8010b0 0x0a02
+;REG32(MC_DC12) = 0x000001C8;
+ 0xbf8010c0 0x1c8
+;REG32(MC_DC13) = 0x00000001;
+ 0xbf8010d0 0x1
+;REG32(MC_DC14) = 0x00000000;
+ 0xbf8010e0 0x0
+;REG32(MC_DC15) = 0x00000F5F;
+; 0xbf8010f0 0xf5f
+; 0xbf8010f0 0xf3c
+ 0xbf8010f0 0x130
+;REG32(MC_DC16) = 0x0000C800;
+ 0xbf801100 0xc800
+;REG32(MC_DC17) = 0x0000000D;
+; 0xbf801110 0xd
+ 0xbf801110 0xd
+;REG32(MC_DC18) = 0x00000300;
+; 0xbf801120 0x300
+ 0xbf801120 0x301
+;REG32(MC_DC19) = 0x00000300;
+; 0xbf801130 0x300
+ 0xbf801130 0x200
+;REG32(MC_DC20) = 0x00000A04;
+; 0xbf801140 0xa04
+ 0xbf801140 0xa03
+;REG32(MC_DC21) = 0x00001c00;
+; 0xbf801150 0xd00
+; 0xbf801150 0x1f00
+ 0xbf801150 0x1b00
+;REG32(MC_DC22) = 0x00001E1E;
+; 0xbf801160 0xd0d
+; 0xbf801160 0x1f1f
+ 0xbf801160 0x1b1b
+;REG32(MC_DC23) = 0x00000000;
+ 0xbf801170 0x0
+;//Disable ECC
+;REG32(MC_DC24) = 0x0000007F;
+; 0xbf801180 0x7f
+; 0xbf801180 0x062
+; 0xbf801180 0x37f
+ 0xbf801180 0x59
+;REG32(MC_DC25) = 0x00000000;
+ 0xbf801190 0x0
+;REG32(MC_DC26) = 0x00000000;
+ 0xbf8011a0 0x0
+;REG32(MC_DC27) = 0x00000000;
+ 0xbf8011b0 0x0
+;REG32(MC_DC28) = 0x00000A24;
+; 0xbf8011c0 0xa24
+ 0xbf8011c0 0x510
+;REG32(MC_DC29) = 0x00002D89;
+; 0xbf8011d0 0x2d89
+; 0xbf8011d0 0x2d92
+ 0xbf8011d0 0x4e20
+;REG32(MC_DC30) = 0x00000022;
+; 0xbf8011e0 0x8300
+ 0xbf8011e0 0x8235
+;REG32(MC_DC31) = 0x00000000;
+ 0xbf8011f0 0x0
+;REG32(MC_DC32) = 0x00000000;
+ 0xbf801200 0x0
+;REG32(MC_DC33) = 0x00000000;
+ 0xbf801210 0x0
+;REG32(MC_DC34) = 0x00000000;
+ 0xbf801220 0x0
+;REG32(MC_DC35) = 0x00000000;
+ 0xbf801230 0x0
+;REG32(MC_DC36) = 0x00000000;
+ 0xbf801240 0x0
+;REG32(MC_DC37) = 0x00000000;
+ 0xbf801250 0x0
+;REG32(MC_DC38) = 0x00000000;
+ 0xbf801260 0x0
+;REG32(MC_DC39) = 0x00000000;
+ 0xbf801270 0x0
+;REG32(MC_DC40) = 0x00000000;
+ 0xbf801280 0x0
+;REG32(MC_DC41) = 0x00000000;
+ 0xbf801290 0x0
+;REG32(MC_DC42) = 0x00000000;
+ 0xbf8012a0 0x0
+;REG32(MC_DC43) = 0x00000000;
+ 0xbf8012b0 0x0
+;REG32(MC_DC44) = 0x00000000;
+ 0xbf8012c0 0x0
+;REG32(MC_DC45) = 0x00000600;
+ 0xbf8012d0 0x500
+;REG32(MC_DC46) = 0x00000000;
+ 0xbf8012e0 0x0
+
+ 0xbf800060 0x05
+ 0xbf801030 0x100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
+BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
+
+BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
COBJS-y += board.o athrs26_phy.o
SOBJS = lowlevel_init.o pmuenable.o
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
+BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
+
+BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
+
+SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
+BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
+
+
+all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
+ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * (C) Copyright 2010 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
+ *
+ * (C) Copyright 2007
+ * Vlad Lungu vlad.lungu@windriver.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t bootstrap_initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return CONFIG_SYS_MAX_RAM;
+}
+
+int bootstrap_checkboard(void)
+{
+ return 0;
+}
+
+int bootstrap_misc_init_r(void)
+{
+ set_io_port_base(0);
+ return 0;
+}
/* Forward references */
BOOL athrs26_phy_is_link_alive(int phyUnit);
-static uint32_t athrs26_reg_read(uint16_t reg_addr);
+//static uint32_t athrs26_reg_read(uint16_t reg_addr);
static void athrs26_reg_write(uint16_t reg_addr,
uint32_t reg_val);
* FALSE --> link is down
*/
-void athrs26_reg_init()
+void athrs26_reg_init(void)
{
athrs26_reg_write(0x200, 0x200);
#endif
-static uint32_t
+/*static uint32_t
athrs26_reg_read(uint16_t reg_addr)
{
#ifndef CFG_ATHRHDR_REG
uint32_t phy_addr;
uint8_t phy_reg;
- /* configure register high address */
phy_addr = 0x18;
phy_reg = 0x0;
- phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
+ phy_val = (reg_word_addr >> 8) & 0x1ff;
phy_reg_write (0, phy_addr, phy_reg, phy_val);
- /* read register with low address */
- phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
- phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address*/
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
+ phy_reg = reg_word_addr & 0x1f;
phy_reg_read(0, phy_addr, phy_reg, &phy_val);
return phy_val;
return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
#endif
}
-
+*/
static void
athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
{
setenv("bootcmd", "httpd");
}
#endif
-
+#ifdef CONFIG_ARV4525
+ *DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
+ *DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
+ *DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
+ *DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
+ *DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
+#endif
}
int checkboard (void)
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
-#
-# Danube board with MIPS 24Kc CPU core
-#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-ifdef CONFIG_LZMA_BOOTSTRAP
-
-ifdef BUILD_BOOTSTRAP
-
-$(info BUILD_BOOTSTRAP )
-#TEXT_BASE = 0xB0000000
-TEXT_BASE = 0x80010000
-
-else # BUILD_BOOTSTRAP
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0x80040000 )
-TEXT_BASE = 0x80040000
-endif
-
-endif # BUILD_BOOTSTRAP
-
+ifdef CONFIG_BOOTSTRAP
+TEXT_BASE = 0x80001000
+CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
+CONFIG_SYS_RAMBOOT = y
else
-ifdef BUILD_BOOTSTRAP
-$(error BUILD_BOOTSTRAP but not enabled in config)
-endif
-
ifndef TEXT_BASE
-## Standard: boot from ebu
$(info redefine TEXT_BASE = 0xB0000000 )
TEXT_BASE = 0xB0000000
-## For testing: boot from RAM
-# TEXT_BASE = 0x80100000
endif
-endif # CONFIG_LZMA_BOOTSTRAP
+endif
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1700
-#define MC_DC22_VALUE 0x1717
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4e20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134 /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5b /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4e20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0xc0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x100
-#define MC_DC4_VALUE 0xd0f
-#define MC_DC5_VALUE 0x204
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0xd47
-#define MC_DC22_VALUE 0xd0d
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x2040
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-#define MC_DC46_VALUE 0x0
--- /dev/null
+/*
+ * Memory sub-system initialization code for Danube board.
+ * Andre Messerschmidt
+ * Copyright (c) 2005 Infineon Technologies AG
+ *
+ * Based on Inca-IP code
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* History:
+ peng liu May 25, 2006, for PLL setting after reset, 05252006
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#if defined(CONFIG_USE_DDR_PSC_32)
+#include "ddr_settings_psc_32.h"
+#define DDR166
+#elif defined(CONFIG_USE_DDR_PSC_64)
+#include "ddr_settings_psc_64.h"
+#define DDR166
+#else
+#error "missing definition for RAM"
+#endif
+
+#define EBU_MODUL_BASE 0xBE105300
+#define EBU_CLC(value) 0x0000(value)
+#define EBU_CON(value) 0x0010(value)
+#define EBU_ADDSEL0(value) 0x0020(value)
+#define EBU_ADDSEL1(value) 0x0024(value)
+#define EBU_ADDSEL2(value) 0x0028(value)
+#define EBU_ADDSEL3(value) 0x002C(value)
+#define EBU_BUSCON0(value) 0x0060(value)
+#define EBU_BUSCON1(value) 0x0064(value)
+#define EBU_BUSCON2(value) 0x0068(value)
+#define EBU_BUSCON3(value) 0x006C(value)
+
+#define MC_MODUL_BASE 0xBF800000
+#define MC_ERRCAUSE(value) 0x0010(value)
+#define MC_ERRADDR(value) 0x0020(value)
+#define MC_CON(value) 0x0060(value)
+
+#define MC_SRAM_ENABLE 0x00000004
+#define MC_SDRAM_ENABLE 0x00000002
+#define MC_DDRRAM_ENABLE 0x00000001
+
+#define MC_SDR_MODUL_BASE 0xBF800200
+#define MC_IOGP(value) 0x0000(value)
+#define MC_CTRLENA(value) 0x0010(value)
+#define MC_MRSCODE(value) 0x0020(value)
+#define MC_CFGDW(value) 0x0030(value)
+#define MC_CFGPB0(value) 0x0040(value)
+#define MC_LATENCY(value) 0x0080(value)
+#define MC_TREFRESH(value) 0x0090(value)
+#define MC_SELFRFSH(value) 0x00A0(value)
+
+#define MC_DDR_MODUL_BASE 0xBF801000
+#define MC_DC00(value) 0x0000(value)
+#define MC_DC01(value) 0x0010(value)
+#define MC_DC02(value) 0x0020(value)
+#define MC_DC03(value) 0x0030(value)
+#define MC_DC04(value) 0x0040(value)
+#define MC_DC05(value) 0x0050(value)
+#define MC_DC06(value) 0x0060(value)
+#define MC_DC07(value) 0x0070(value)
+#define MC_DC08(value) 0x0080(value)
+#define MC_DC09(value) 0x0090(value)
+#define MC_DC10(value) 0x00A0(value)
+#define MC_DC11(value) 0x00B0(value)
+#define MC_DC12(value) 0x00C0(value)
+#define MC_DC13(value) 0x00D0(value)
+#define MC_DC14(value) 0x00E0(value)
+#define MC_DC15(value) 0x00F0(value)
+#define MC_DC16(value) 0x0100(value)
+#define MC_DC17(value) 0x0110(value)
+#define MC_DC18(value) 0x0120(value)
+#define MC_DC19(value) 0x0130(value)
+#define MC_DC20(value) 0x0140(value)
+#define MC_DC21(value) 0x0150(value)
+#define MC_DC22(value) 0x0160(value)
+#define MC_DC23(value) 0x0170(value)
+#define MC_DC24(value) 0x0180(value)
+#define MC_DC25(value) 0x0190(value)
+#define MC_DC26(value) 0x01A0(value)
+#define MC_DC27(value) 0x01B0(value)
+#define MC_DC28(value) 0x01C0(value)
+#define MC_DC29(value) 0x01D0(value)
+#define MC_DC30(value) 0x01E0(value)
+#define MC_DC31(value) 0x01F0(value)
+#define MC_DC32(value) 0x0200(value)
+#define MC_DC33(value) 0x0210(value)
+#define MC_DC34(value) 0x0220(value)
+#define MC_DC35(value) 0x0230(value)
+#define MC_DC36(value) 0x0240(value)
+#define MC_DC37(value) 0x0250(value)
+#define MC_DC38(value) 0x0260(value)
+#define MC_DC39(value) 0x0270(value)
+#define MC_DC40(value) 0x0280(value)
+#define MC_DC41(value) 0x0290(value)
+#define MC_DC42(value) 0x02A0(value)
+#define MC_DC43(value) 0x02B0(value)
+#define MC_DC44(value) 0x02C0(value)
+#define MC_DC45(value) 0x02D0(value)
+#define MC_DC46(value) 0x02E0(value)
+
+#define RCU_OFFSET 0xBF203000
+#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
+#define RCU_STS (RCU_OFFSET + 0x0014)
+
+#define CGU_OFFSET 0xBF103000
+#define PLL0_CFG (CGU_OFFSET + 0x0004)
+#define PLL1_CFG (CGU_OFFSET + 0x0008)
+#define PLL2_CFG (CGU_OFFSET + 0x000C)
+#define CGU_SYS (CGU_OFFSET + 0x0010)
+#define CGU_UPDATE (CGU_OFFSET + 0x0014)
+#define IF_CLK (CGU_OFFSET + 0x0018)
+#define CGU_SMD (CGU_OFFSET + 0x0020)
+#define CGU_CT1SR (CGU_OFFSET + 0x0028)
+#define CGU_CT2SR (CGU_OFFSET + 0x002C)
+#define CGU_PCMCR (CGU_OFFSET + 0x0030)
+#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
+#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
+#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
+#define CLK_MEASURE (CGU_OFFSET + 0x003C)
+
+//05252006
+#define pll0_35MHz_CONFIG 0x9D861059
+#define pll1_35MHz_CONFIG 0x1A260CD9
+#define pll2_35MHz_CONFIG 0x8000f1e5
+#define pll0_36MHz_CONFIG 0x1000125D
+#define pll1_36MHz_CONFIG 0x1B1E0C99
+#define pll2_36MHz_CONFIG 0x8002f2a1
+//05252006
+
+//06063001-joelin disable the PCI CFRAME mask -start
+/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
+But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
+
+The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
+The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
+*/
+#define PCI_CR_PR_OFFSET 0xBE105400
+#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
+#define PCI_CONFIG_SPACE 0xB7000000
+#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
+//06063001-joelin disable the PCI CFRAME mask -end
+ .set noreorder
+
+
+/*
+ * void ebu_init(void)
+ */
+ .globl ebu_init
+ .ent ebu_init
+ebu_init:
+
+#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
+ defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
+ defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
+ defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
+
+ li t1, EBU_MODUL_BASE
+#if defined(CONFIG_EBU_ADDSEL0)
+ li t2, CONFIG_EBU_ADDSEL0
+ sw t2, EBU_ADDSEL0(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL1)
+ li t2, CONFIG_EBU_ADDSEL1
+ sw t2, EBU_ADDSEL1(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL2)
+ li t2, CONFIG_EBU_ADDSEL2
+ sw t2, EBU_ADDSEL2(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL3)
+ li t2, CONFIG_EBU_ADDSEL3
+ sw t2, EBU_ADDSEL3(t1)
+#endif
+
+#if defined(CONFIG_EBU_BUSCON0)
+ li t2, CONFIG_EBU_BUSCON0
+ sw t2, EBU_BUSCON0(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON1)
+ li t2, CONFIG_EBU_BUSCON1
+ sw t2, EBU_BUSCON1(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON2)
+ li t2, CONFIG_EBU_BUSCON2
+ sw t2, EBU_BUSCON2(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON3)
+ li t2, CONFIG_EBU_BUSCON3
+ sw t2, EBU_BUSCON3(t1)
+#endif
+
+#endif
+
+ j ra
+ nop
+
+ .end ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl cgu_init
+ .ent cgu_init
+cgu_init:
+ li t2, CGU_SYS
+ lw t2,0(t2)
+ beq t2,a0,freq_up2date
+ nop
+
+ li t2, RCU_STS
+ lw t2, 0(t2)
+ and t2,0x00020000
+ beq t2,0x00020000,boot_36MHZ
+ nop
+//05252006
+ li t1, PLL0_CFG
+ li t2, pll0_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL1_CFG
+ li t2, pll1_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL2_CFG
+ li t2, pll2_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, CGU_SYS
+ sw a0,0(t1)
+ li t1, RCU_RST_REQ
+ li t2, 0x40000008
+ sw t2,0(t1)
+ b wait_reset
+ nop
+boot_36MHZ:
+ li t1, PLL0_CFG
+ li t2, pll0_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL1_CFG
+ li t2, pll1_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL2_CFG
+ li t2, pll2_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, CGU_SYS
+ sw a0,0(t1)
+ li t1, RCU_RST_REQ
+ li t2, 0x40000008
+ sw t2,0(t1)
+//05252006
+
+wait_reset:
+ b wait_reset
+ nop
+freq_up2date:
+ j ra
+ nop
+
+ .end cgu_init
+
+#ifndef CONFIG_USE_DDR_RAM
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl sdram_init
+ .ent sdram_init
+sdram_init:
+
+ /* SDRAM Initialization
+ */
+ li t1, MC_MODUL_BASE
+
+ /* Clear Error log registers */
+ sw zero, MC_ERRCAUSE(t1)
+ sw zero, MC_ERRADDR(t1)
+
+ /* Enable SDRAM module in memory controller */
+ li t3, MC_SDRAM_ENABLE
+ lw t2, MC_CON(t1)
+ or t3, t2, t3
+ sw t3, MC_CON(t1)
+
+ li t1, MC_SDR_MODUL_BASE
+
+ /* disable the controller */
+ li t2, 0
+ sw t2, MC_CTRLENA(t1)
+
+ li t2, 0x822
+ sw t2, MC_IOGP(t1)
+
+ li t2, 0x2
+ sw t2, MC_CFGDW(t1)
+
+ /* Set CAS Latency */
+ li t2, 0x00000020
+ sw t2, MC_MRSCODE(t1)
+
+ /* Set CS0 to SDRAM parameters */
+ li t2, 0x000014d8
+ sw t2, MC_CFGPB0(t1)
+
+ /* Set SDRAM latency parameters */
+ li t2, 0x00036325; /* BC PC100 */
+ sw t2, MC_LATENCY(t1)
+
+ /* Set SDRAM refresh rate */
+ li t2, 0x00000C30
+ sw t2, MC_TREFRESH(t1)
+
+ /* Clear Power-down registers */
+ sw zero, MC_SELFRFSH(t1)
+
+ /* Finally enable the controller */
+ li t2, 1
+ sw t2, MC_CTRLENA(t1)
+
+ j ra
+ nop
+
+ .end sdram_init
+
+#endif /* !CONFIG_USE_DDR_RAM */
+
+#ifdef CONFIG_USE_DDR_RAM
+/*
+ * void ddrram_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl ddrram_init
+ .ent ddrram_init
+ddrram_init:
+
+ /* DDR-DRAM Initialization
+ */
+ li t1, MC_MODUL_BASE
+
+ /* Clear Error log registers */
+ sw zero, MC_ERRCAUSE(t1)
+ sw zero, MC_ERRADDR(t1)
+
+ /* Enable DDR module in memory controller */
+ li t3, MC_DDRRAM_ENABLE
+ lw t2, MC_CON(t1)
+ or t3, t2, t3
+ sw t3, MC_CON(t1)
+
+ li t1, MC_DDR_MODUL_BASE
+
+ /* Write configuration to DDR controller registers */
+ li t2, MC_DC0_VALUE
+ sw t2, MC_DC00(t1)
+
+ li t2, MC_DC1_VALUE
+ sw t2, MC_DC01(t1)
+
+ li t2, MC_DC2_VALUE
+ sw t2, MC_DC02(t1)
+
+ li t2, MC_DC3_VALUE
+ sw t2, MC_DC03(t1)
+
+ li t2, MC_DC4_VALUE
+ sw t2, MC_DC04(t1)
+
+ li t2, MC_DC5_VALUE
+ sw t2, MC_DC05(t1)
+
+ li t2, MC_DC6_VALUE
+ sw t2, MC_DC06(t1)
+
+ li t2, MC_DC7_VALUE
+ sw t2, MC_DC07(t1)
+
+ li t2, MC_DC8_VALUE
+ sw t2, MC_DC08(t1)
+
+ li t2, MC_DC9_VALUE
+ sw t2, MC_DC09(t1)
+
+ li t2, MC_DC10_VALUE
+ sw t2, MC_DC10(t1)
+
+ li t2, MC_DC11_VALUE
+ sw t2, MC_DC11(t1)
+
+ li t2, MC_DC12_VALUE
+ sw t2, MC_DC12(t1)
+
+ li t2, MC_DC13_VALUE
+ sw t2, MC_DC13(t1)
+
+ li t2, MC_DC14_VALUE
+ sw t2, MC_DC14(t1)
+
+ li t2, MC_DC15_VALUE
+ sw t2, MC_DC15(t1)
+
+ li t2, MC_DC16_VALUE
+ sw t2, MC_DC16(t1)
+
+ li t2, MC_DC17_VALUE
+ sw t2, MC_DC17(t1)
+
+ li t2, MC_DC18_VALUE
+ sw t2, MC_DC18(t1)
+
+ li t2, MC_DC19_VALUE
+ sw t2, MC_DC19(t1)
+
+ li t2, MC_DC20_VALUE
+ sw t2, MC_DC20(t1)
+
+ li t2, MC_DC21_VALUE
+ sw t2, MC_DC21(t1)
+
+ li t2, MC_DC22_VALUE
+ sw t2, MC_DC22(t1)
+
+ li t2, MC_DC23_VALUE
+ sw t2, MC_DC23(t1)
+
+ li t2, MC_DC24_VALUE
+ sw t2, MC_DC24(t1)
+
+ li t2, MC_DC25_VALUE
+ sw t2, MC_DC25(t1)
+
+ li t2, MC_DC26_VALUE
+ sw t2, MC_DC26(t1)
+
+ li t2, MC_DC27_VALUE
+ sw t2, MC_DC27(t1)
+
+ li t2, MC_DC28_VALUE
+ sw t2, MC_DC28(t1)
+
+ li t2, MC_DC29_VALUE
+ sw t2, MC_DC29(t1)
+
+ li t2, MC_DC30_VALUE
+ sw t2, MC_DC30(t1)
+
+ li t2, MC_DC31_VALUE
+ sw t2, MC_DC31(t1)
+
+ li t2, MC_DC32_VALUE
+ sw t2, MC_DC32(t1)
+
+ li t2, MC_DC33_VALUE
+ sw t2, MC_DC33(t1)
+
+ li t2, MC_DC34_VALUE
+ sw t2, MC_DC34(t1)
+
+ li t2, MC_DC35_VALUE
+ sw t2, MC_DC35(t1)
+
+ li t2, MC_DC36_VALUE
+ sw t2, MC_DC36(t1)
+
+ li t2, MC_DC37_VALUE
+ sw t2, MC_DC37(t1)
+
+ li t2, MC_DC38_VALUE
+ sw t2, MC_DC38(t1)
+
+ li t2, MC_DC39_VALUE
+ sw t2, MC_DC39(t1)
+
+ li t2, MC_DC40_VALUE
+ sw t2, MC_DC40(t1)
+
+ li t2, MC_DC41_VALUE
+ sw t2, MC_DC41(t1)
+
+ li t2, MC_DC42_VALUE
+ sw t2, MC_DC42(t1)
+
+ li t2, MC_DC43_VALUE
+ sw t2, MC_DC43(t1)
+
+ li t2, MC_DC44_VALUE
+ sw t2, MC_DC44(t1)
+
+ li t2, MC_DC45_VALUE
+ sw t2, MC_DC45(t1)
+
+ li t2, MC_DC46_VALUE
+ sw t2, MC_DC46(t1)
+
+ li t2, 0x00000100
+ sw t2, MC_DC03(t1)
+
+ j ra
+ nop
+
+ .end ddrram_init
+#endif /* CONFIG_USE_DDR_RAM */
+
+ .globl lowlevel_init
+ .ent lowlevel_init
+lowlevel_init:
+ /* EBU, CGU and SDRAM/DDR-RAM Initialization.
+ */
+ move t0, ra
+ /* We rely on the fact that non of the following ..._init() functions
+ * modify t0
+ */
+#if defined(DDR166)
+ /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
+ li a0,0xe8
+#elif defined(DDR133)
+ /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
+ li a0,0xe9
+#else /* defined(DDR111) */
+ /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
+ li a0,0xea
+#endif
+ bal cgu_init
+ nop
+
+ bal ebu_init
+ nop
+
+//06063001-joelin disable the PCI CFRAME mask-start
+#ifdef DISABLE_CFRAME
+ li t1, PCI_CR_PCI //mw bf103034 80000000
+ li t2, 0x80000000
+ sw t2,0(t1)
+
+ li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
+ li t2, 0x103
+ sw t2,0(t1)
+
+ li t1, CS_CFM //mw b700006c 0
+ li t2, 0x00
+ sw t2, 0(t1)
+
+ li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
+ li t2, 0x1000103
+ sw t2, 0(t1)
+#endif
+//06063001-joelin disable the PCI CFRAME mask-end
+
+#ifdef CONFIG_USE_DDR_RAM
+ bal ddrram_init
+ nop
+#else
+ bal sdram_init
+ nop
+#endif
+ move ra, t0
+ j ra
+ nop
+
+ .end lowlevel_init
#include <version.h>
#include <asm/regdef.h>
-#if 0
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
+#if defined(CONFIG_USE_DDR_PSC_32)
+#include "ddr_settings_psc_32.h"
#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
+#elif defined(CONFIG_USE_DDR_PSC_64)
+#include "ddr_settings_psc_64.h"
#define DDR166
#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#else
-
-#include "ddr_settings_psc_166.h"
-#define DDR166
-
-#endif
-
-#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
+#error "missing definition for RAM"
#endif
#define EBU_MODUL_BASE 0xBE105300
.ent ebu_init
ebu_init:
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
- defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
- defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
- defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
- li t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
- li t2, CONFIG_EBU_ADDSEL0
- sw t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
- li t2, CONFIG_EBU_ADDSEL1
- sw t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
- li t2, CONFIG_EBU_ADDSEL2
- sw t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
- li t2, CONFIG_EBU_ADDSEL3
- sw t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
- li t2, CONFIG_EBU_BUSCON0
- sw t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
- li t2, CONFIG_EBU_BUSCON1
- sw t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
- li t2, CONFIG_EBU_BUSCON2
- sw t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
- li t2, CONFIG_EBU_BUSCON3
- sw t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
j ra
nop
.end cgu_init
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
- .globl sdram_init
- .ent sdram_init
-sdram_init:
-
- /* SDRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable SDRAM module in memory controller */
- li t3, MC_SDRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_SDR_MODUL_BASE
-
- /* disable the controller */
- li t2, 0
- sw t2, MC_CTRLENA(t1)
-
- li t2, 0x822
- sw t2, MC_IOGP(t1)
-
- li t2, 0x2
- sw t2, MC_CFGDW(t1)
-
- /* Set CAS Latency */
- li t2, 0x00000020
- sw t2, MC_MRSCODE(t1)
-
- /* Set CS0 to SDRAM parameters */
- li t2, 0x000014d8
- sw t2, MC_CFGPB0(t1)
-
- /* Set SDRAM latency parameters */
- li t2, 0x00036325; /* BC PC100 */
- sw t2, MC_LATENCY(t1)
-
- /* Set SDRAM refresh rate */
- li t2, 0x00000C30
- sw t2, MC_TREFRESH(t1)
-
- /* Clear Power-down registers */
- sw zero, MC_SELFRFSH(t1)
-
- /* Finally enable the controller */
- li t2, 1
- sw t2, MC_CTRLENA(t1)
-
- j ra
- nop
-
- .end sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
- .globl ddrram_init
- .ent ddrram_init
-ddrram_init:
-
- /* DDR-DRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable DDR module in memory controller */
- li t3, MC_DDRRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_DDR_MODUL_BASE
-
- /* Write configuration to DDR controller registers */
- li t2, MC_DC0_VALUE
- sw t2, MC_DC00(t1)
-
- li t2, MC_DC1_VALUE
- sw t2, MC_DC01(t1)
-
- li t2, MC_DC2_VALUE
- sw t2, MC_DC02(t1)
-
- li t2, MC_DC3_VALUE
- sw t2, MC_DC03(t1)
-
- li t2, MC_DC4_VALUE
- sw t2, MC_DC04(t1)
-
- li t2, MC_DC5_VALUE
- sw t2, MC_DC05(t1)
-
- li t2, MC_DC6_VALUE
- sw t2, MC_DC06(t1)
-
- li t2, MC_DC7_VALUE
- sw t2, MC_DC07(t1)
-
- li t2, MC_DC8_VALUE
- sw t2, MC_DC08(t1)
-
- li t2, MC_DC9_VALUE
- sw t2, MC_DC09(t1)
-
- li t2, MC_DC10_VALUE
- sw t2, MC_DC10(t1)
-
- li t2, MC_DC11_VALUE
- sw t2, MC_DC11(t1)
-
- li t2, MC_DC12_VALUE
- sw t2, MC_DC12(t1)
-
- li t2, MC_DC13_VALUE
- sw t2, MC_DC13(t1)
-
- li t2, MC_DC14_VALUE
- sw t2, MC_DC14(t1)
-
- li t2, MC_DC15_VALUE
- sw t2, MC_DC15(t1)
-
- li t2, MC_DC16_VALUE
- sw t2, MC_DC16(t1)
-
- li t2, MC_DC17_VALUE
- sw t2, MC_DC17(t1)
-
- li t2, MC_DC18_VALUE
- sw t2, MC_DC18(t1)
-
- li t2, MC_DC19_VALUE
- sw t2, MC_DC19(t1)
-
- li t2, MC_DC20_VALUE
- sw t2, MC_DC20(t1)
-
- li t2, MC_DC21_VALUE
- sw t2, MC_DC21(t1)
-
- li t2, MC_DC22_VALUE
- sw t2, MC_DC22(t1)
-
- li t2, MC_DC23_VALUE
- sw t2, MC_DC23(t1)
-
- li t2, MC_DC24_VALUE
- sw t2, MC_DC24(t1)
-
- li t2, MC_DC25_VALUE
- sw t2, MC_DC25(t1)
-
- li t2, MC_DC26_VALUE
- sw t2, MC_DC26(t1)
-
- li t2, MC_DC27_VALUE
- sw t2, MC_DC27(t1)
-
- li t2, MC_DC28_VALUE
- sw t2, MC_DC28(t1)
-
- li t2, MC_DC29_VALUE
- sw t2, MC_DC29(t1)
-
- li t2, MC_DC30_VALUE
- sw t2, MC_DC30(t1)
-
- li t2, MC_DC31_VALUE
- sw t2, MC_DC31(t1)
-
- li t2, MC_DC32_VALUE
- sw t2, MC_DC32(t1)
-
- li t2, MC_DC33_VALUE
- sw t2, MC_DC33(t1)
-
- li t2, MC_DC34_VALUE
- sw t2, MC_DC34(t1)
-
- li t2, MC_DC35_VALUE
- sw t2, MC_DC35(t1)
-
- li t2, MC_DC36_VALUE
- sw t2, MC_DC36(t1)
-
- li t2, MC_DC37_VALUE
- sw t2, MC_DC37(t1)
-
- li t2, MC_DC38_VALUE
- sw t2, MC_DC38(t1)
-
- li t2, MC_DC39_VALUE
- sw t2, MC_DC39(t1)
-
- li t2, MC_DC40_VALUE
- sw t2, MC_DC40(t1)
-
- li t2, MC_DC41_VALUE
- sw t2, MC_DC41(t1)
-
- li t2, MC_DC42_VALUE
- sw t2, MC_DC42(t1)
-
- li t2, MC_DC43_VALUE
- sw t2, MC_DC43(t1)
-
- li t2, MC_DC44_VALUE
- sw t2, MC_DC44(t1)
-
- li t2, MC_DC45_VALUE
- sw t2, MC_DC45(t1)
-
- li t2, MC_DC46_VALUE
- sw t2, MC_DC46(t1)
-
- li t2, 0x00000100
- sw t2, MC_DC03(t1)
-
- j ra
- nop
-
- .end ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
-#if defined(CONFIG_SYS_EBU_BOOT)
-#if defined(DDR166)
- /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
- li a0,0xe8
-#elif defined(DDR133)
- /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
- li a0,0xe9
-#else /* defined(DDR111) */
- /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
- li a0,0xea
-#endif
- bal cgu_init
- nop
-#endif /* CONFIG_SYS_EBU_BOOT */
bal ebu_init
nop
#endif
//06063001-joelin disable the PCI CFRAME mask-end
-#ifdef CONFIG_SYS_EBU_BOOT
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_USE_DDR_RAM
- bal ddrram_init
- nop
-#else
- bal sdram_init
- nop
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-#endif /* CONFIG_SYS_EBU_BOOT */
-
move ra, t0
j ra
nop
--- /dev/null
+/*
+ * (C) Copyright 2010 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = .;
+ _gp = ALIGN(16) +0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ . = .;
+ . = ALIGN(4);
+ .payload : { *(.payload) }
+ . = ALIGN(4);
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) . = ALIGN(4); }
+ uboot_end = .;
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ar9.h>
+
+ulong ifx_get_ddr_hz(void)
+{
+ switch((*AR9_CGU_SYS) & 0x05) {
+ case 0x01:
+ case 0x05:
+ return CLOCK_111M;
+
+ case 0x00:
+ case 0x04:
+ return CLOCK_166M;
+ }
+
+ return 0;
+}
+
+ulong ifx_get_cpuclk(void)
+{
+ switch((*AR9_CGU_SYS) & 0x05) {
+ case 0x00:
+ case 0x01:
+ return CLOCK_333M;
+
+ case 0x04:
+ return CLOCK_166M;
+
+ case 0x05:
+ return CLOCK_111M;
+ }
+
+ return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ unsigned int ddr_clock=ifx_get_ddr_hz();
+ if((*AR9_CGU_SYS) & 0x40){
+ return ddr_clock/2;
+ } else {
+ return ddr_clock;
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/danube.h>
+
+ulong ifx_get_ddr_hz(void)
+{
+ static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333};
+ return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)];
+}
+
+ulong ifx_get_cpuclk(void)
+{
+#ifdef CONFIG_USE_EMULATOR
+ return EMULATOR_CPU_SPEED;
+#else //NOT CONFIG_USE_EMULATOR
+ unsigned int ddr_clock=ifx_get_ddr_hz();
+ switch((*DANUBE_CGU_SYS) & 0xc){
+ case 0:
+ default:
+ return 323333333;
+ case 4:
+ return ddr_clock;
+ case 8:
+ return ddr_clock << 1;
+ }
+#endif
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+#ifdef CONFIG_USE_EMULATOR
+ unsigned int clkCPU;
+ clkCPU = ifx_get_cpuclk();
+ return clkCPU >> 2;
+#else //NOT CONFIG_USE_EMULATOR
+ unsigned int ddr_clock=ifx_get_ddr_hz();
+ if ((*DANUBE_CGU_SYS) & 0x40){
+ return ddr_clock >> 1;
+ }
+ return ddr_clock;
+#endif
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2009
+ * Infineon Technologies AG, http://www.infineon.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+
+#include "ifx_asc.h"
+
+#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
+#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
+#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
+
+#undef DEBUG_ASC_RAW
+#ifdef DEBUG_ASC_RAW
+#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
+#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
+
+/*
+ * FDV fASC
+ * BaudRate = ----- * --------------------
+ * 512 16 * (ReloadValue+1)
+ */
+
+/*
+ * FDV fASC
+ * ReloadValue = ( ----- * --------------- ) - 1
+ * 512 16 * BaudRate
+ */
+static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
+{
+ u32 clock = fasc / 16;
+
+ u32 fdv; /* best fdv */
+ u32 reload = 0; /* best reload */
+ u32 diff; /* smallest diff */
+ u32 idiff; /* current diff */
+ u32 ireload; /* current reload */
+ u32 i; /* current fdv */
+ u32 result; /* current resulting baudrate */
+
+ if (clock > 0x7FFFFF)
+ clock /= 512;
+ else
+ baudrate *= 512;
+
+ fdv = 512; /* start with 1:1 fraction */
+ diff = baudrate; /* highest possible */
+
+ /* i is the test fdv value -- start with the largest possible */
+ for (i = 512; i > 0; i--)
+ {
+ ireload = (clock * i) / baudrate;
+ if (ireload < 1)
+ break; /* already invalid */
+ result = (clock * i) / ireload;
+
+ idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
+ if (idiff == 0)
+ {
+ fdv = i;
+ reload = ireload;
+ break; /* can't do better */
+ }
+ else if (idiff < diff)
+ {
+ fdv = i; /* best so far */
+ reload = ireload;
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pfdv = (fdv == 512) ? 0 : fdv;
+ *preload = reload - 1;
+}
+
+
+void serial_setbrg (void)
+{
+ u32 ReloadValue, fdv;
+
+ serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
+
+ /* Disable Baud Rate Generator; BG should only be written when R=0 */
+ CLEAR_BIT(asc_con, ASCCON_R);
+
+ /* Enable Fractional Divider */
+ SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
+
+ /* Set fractional divider value */
+ asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
+
+ /* Set reload value in BG */
+ asc_writel(asc_bg, ReloadValue);
+
+ /* Enable Baud Rate Generator */
+ SET_BIT(asc_con, ASCCON_R); /* R = 1 */
+}
+
+
+int serial_init (void)
+{
+
+ /* and we have to set CLC register*/
+ CLEAR_BIT(asc_clc, ASCCLC_DISS);
+ SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+ /* initialy we are in async mode */
+ asc_writel(asc_con, ASCCON_M_8ASYNC);
+
+ /* select input port */
+ asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
+
+ /* TXFIFO's filling level */
+ SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
+ ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
+ /* enable TXFIFO */
+ SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
+
+ /* RXFIFO's filling level */
+ SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
+ ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
+ /* enable RXFIFO */
+ SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
+
+ /* set baud rate */
+ serial_setbrg();
+
+ /* enable error signals & Receiver enable */
+ SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
+
+ return 0;
+}
+
+
+void serial_putc (const char c)
+{
+ u32 txFl = 0;
+#ifdef DEBUG_ASC_RAW
+ static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
+ *debug++=c;
+#endif
+ if (c == '\n')
+ serial_putc ('\r');
+ /* check do we have a free space in the TX FIFO */
+ /* get current filling level */
+ do {
+ txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+ }
+ while ( txFl == ASC_TXFIFO_FULL );
+
+ asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
+
+ /* check for errors */
+ if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
+ SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
+ return;
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ char c;
+ while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
+ c = (char)(asc_readl(asc_rbuf) & 0xff);
+
+#ifdef DEBUG_ASC_RAW
+ static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
+ *debug++=c;
+#endif
+ return c;
+}
+
+
+int serial_tstc (void)
+{
+ int res = 1;
+
+ if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
+ res = 0;
+ }
+ return res;
+}
--- /dev/null
+/*****************************************************************************
+ * DANUBE BootROM
+ * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
+ * IFAP DC COM SD
+ *****************************************************************************/
+#ifndef __ASC_H
+#define __ASC_H
+
+/* channel operating modes */
+#define ASCOPT_CSIZE 0x00000003
+#define ASCOPT_CS7 0x00000001
+#define ASCOPT_CS8 0x00000002
+#define ASCOPT_PARENB 0x00000004
+#define ASCOPT_STOPB 0x00000008
+#define ASCOPT_PARODD 0x00000010
+#define ASCOPT_CREAD 0x00000020
+
+#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY 0
+
+#define ASC_TXFIFO_FL 1
+#define ASC_RXFIFO_FL 1
+#define ASC_TXFIFO_FULL 16
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR 0x00000001
+#define ASCCLC_DISS 0x00000002
+#define ASCCLC_RMCMASK 0x0000FF00
+#define ASCCLC_RMCOFFSET 8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK 0x0000000f
+#define ASCCON_M_8ASYNC 0x0
+#define ASCCON_M_8IRDA 0x1
+#define ASCCON_M_7ASYNC 0x2
+#define ASCCON_M_7IRDA 0x3
+#define ASCCON_WLSMASK 0x0000000c
+#define ASCCON_WLSOFFSET 2
+#define ASCCON_WLS_8BIT 0x0
+#define ASCCON_WLS_7BIT 0x1
+#define ASCCON_PEN 0x00000010
+#define ASCCON_ODD 0x00000020
+#define ASCCON_SP 0x00000040
+#define ASCCON_STP 0x00000080
+#define ASCCON_BRS 0x00000100
+#define ASCCON_FDE 0x00000200
+#define ASCCON_ERRCLK 0x00000400
+#define ASCCON_EMMASK 0x00001800
+#define ASCCON_EMOFFSET 11
+#define ASCCON_EM_ECHO_OFF 0x0
+#define ASCCON_EM_ECHO_AB 0x1
+#define ASCCON_EM_ECHO_ON 0x2
+#define ASCCON_LB 0x00002000
+#define ASCCON_ACO 0x00004000
+#define ASCCON_R 0x00008000
+#define ASCCON_PAL 0x00010000
+#define ASCCON_FEN 0x00020000
+#define ASCCON_RUEN 0x00040000
+#define ASCCON_ROEN 0x00080000
+#define ASCCON_TOEN 0x00100000
+#define ASCCON_BEN 0x00200000
+#define ASCCON_TXINV 0x01000000
+#define ASCCON_RXINV 0x02000000
+#define ASCCON_TXMSB 0x04000000
+#define ASCCON_RXMSB 0x08000000
+
+/* STATE register's bits and bitfields */
+#define ASCSTATE_REN 0x00000001
+#define ASCSTATE_PE 0x00010000
+#define ASCSTATE_FE 0x00020000
+#define ASCSTATE_RUE 0x00040000
+#define ASCSTATE_ROE 0x00080000
+#define ASCSTATE_TOE 0x00100000
+#define ASCSTATE_BE 0x00200000
+#define ASCSTATE_TXBVMASK 0x07000000
+#define ASCSTATE_TXBVOFFSET 24
+#define ASCSTATE_TXEOM 0x08000000
+#define ASCSTATE_RXBVMASK 0x70000000
+#define ASCSTATE_RXBVOFFSET 28
+#define ASCSTATE_RXEOM 0x80000000
+
+/* WHBSTATE register's bits and bitfields */
+#define ASCWHBSTATE_CLRREN 0x00000001
+#define ASCWHBSTATE_SETREN 0x00000002
+#define ASCWHBSTATE_CLRPE 0x00000004
+#define ASCWHBSTATE_CLRFE 0x00000008
+#define ASCWHBSTATE_CLRRUE 0x00000010
+#define ASCWHBSTATE_CLRROE 0x00000020
+#define ASCWHBSTATE_CLRTOE 0x00000040
+#define ASCWHBSTATE_CLRBE 0x00000080
+#define ASCWHBSTATE_SETPE 0x00000100
+#define ASCWHBSTATE_SETFE 0x00000200
+#define ASCWHBSTATE_SETRUE 0x00000400
+#define ASCWHBSTATE_SETROE 0x00000800
+#define ASCWHBSTATE_SETTOE 0x00001000
+#define ASCWHBSTATE_SETBE 0x00002000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN 0x0001
+#define ASCABCON_AUREN 0x0002
+#define ASCABCON_ABSTEN 0x0004
+#define ASCABCON_ABDETEN 0x0008
+#define ASCABCON_FCDETEN 0x0010
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK 0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_CLRABEN 0x0001
+#define ASCWHBABCON_SETABEN 0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET 0x0001
+#define ASCABSTAT_FCCDET 0x0002
+#define ASCABSTAT_SCSDET 0x0004
+#define ASCABSTAT_SCCDET 0x0008
+#define ASCABSTAT_DETWAIT 0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET 0x0001
+#define ASCWHBABSTAT_SETFCSDET 0x0002
+#define ASCWHBABSTAT_CLRFCCDET 0x0004
+#define ASCWHBABSTAT_SETFCCDET 0x0008
+#define ASCWHBABSTAT_CLRSCSDET 0x0010
+#define ASCWHBABSTAT_SETSCSDET 0x0020
+#define ASCWHBABSTAT_CLRSCCDET 0x0040
+#define ASCWHBABSTAT_SETSCCDET 0x0080
+#define ASCWHBABSTAT_CLRDETWAIT 0x0100
+#define ASCWHBABSTAT_SETDETWAIT 0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFIFO1 0x00000400
+#define ASCTXFCON_TXFEN 0x0001
+#define ASCTXFCON_TXFFLU 0x0002
+#define ASCTXFCON_TXFITLMASK 0x3F00
+#define ASCTXFCON_TXFITLOFF 8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFIFO1 0x00000400
+#define ASCRXFCON_RXFEN 0x0001
+#define ASCRXFCON_RXFFLU 0x0002
+#define ASCRXFCON_RXFITLMASK 0x3F00
+#define ASCRXFCON_RXFITLOFF 8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK 0x003F
+#define ASCFSTAT_TXFFLMASK 0x3F00
+#define ASCFSTAT_TXFFLOFF 8
+
+typedef struct IfxAsc_s
+{
+ unsigned long asc_clc; /*0x0000*/
+ unsigned long asc_pisel; /*0x0004*/
+ unsigned long asc_id; /*0x0008*/
+ unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
+ unsigned long asc_con; /*0x0010*/
+ unsigned long asc_state; /*0x0014*/
+ unsigned long asc_whbstate; /*0x0018*/
+ unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
+ unsigned long asc_tbuf; /*0x0020*/
+ unsigned long asc_rbuf; /*0x0024*/
+ unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
+ unsigned long asc_abcon; /*0x0030*/
+ unsigned long asc_abstat; /* not used */ /*0x0034*/
+ unsigned long asc_whbabcon; /*0x0038*/
+ unsigned long asc_whbabstat; /* not used */ /*0x003C*/
+ unsigned long asc_rxfcon; /*0x0040*/
+ unsigned long asc_txfcon; /*0x0044*/
+ unsigned long asc_fstat; /*0x0048*/
+ unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
+ unsigned long asc_bg; /*0x0050*/
+ unsigned long asc_bg_timer; /*0x0054*/
+ unsigned long asc_fdv; /*0x0058*/
+ unsigned long asc_pmw; /*0x005C*/
+ unsigned long asc_modcon; /*0x0060*/
+ unsigned long asc_modstat; /*0x0064*/
+ unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
+ unsigned long asc_sfcc; /*0x0070*/
+ unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
+ unsigned long asc_eomcon; /*0x0080*/
+ unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
+ unsigned long asc_dmacon; /*0x00EC*/
+ unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
+ unsigned long asc_irnen; /*0x00F4*/
+ unsigned long asc_irnicr; /*0x00F8*/
+ unsigned long asc_irncr; /*0x00FC*/
+} IfxAsc_t;
+
+
+/* Register access macros */
+#define asc_readl(reg) \
+ readl(&pAsc->reg)
+#define asc_writel(reg,value) \
+ writel((value), &pAsc->reg)
+
+
+#endif /* __ASC_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-/* #define DEBUG */
-
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
- "kernel_addr=0xb0050000\0" \
+ "kernel_addr=0xb0020000\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} \0" \
"update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
"update_openwrt=tftp ${ram_addr} " \
- "${tftppath}openwrt-lantiq-xway-" CONFIG_ARCADYAN "-squashfs.image;" \
+ "${tftppath}" CONFIG_ARCADYAN "-squashfs.image;" \
"era ${kernel_addr} +${filesize};" \
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
//#define CLK_OUT2_25MHZ
#define CONFIG_MII
-#define CONFIG_CMD_MII
+#undef CONFIG_CMD_MII
#define CONFIG_IFX_ASC
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH "/export"
+#ifdef CONFIG_BOOTSTRAP
+#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE
+#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOOTSTRAP_LZMA
+//#define CONFIG_BOOTSTRAP_SERIAL
+#endif
+
+
+
#endif /* __CONFIG_H */
--- /dev/null
+#ifndef __CONFIG_H_3527
+#define __CONFIG_H_3527
+
+#define CONFIG_ARV3527 1
+#define CONFIG_ARCADYAN "ARV3527P"
+
+#define CONFIG_SYS_MAX_RAM 32*1024*1024
+#define CONFIG_USE_DDR_PSC_32 1
+#define CONFIG_SYS_PROMPT "ARV3527 => "
+
+/*#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN 13
+#define CONFIG_BUTTON_LEVEL 0
+*/
+#include "arcadyan-common.h"
+
+#endif
#define CONFIG_ARCADYAN "ARV4518PW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
+#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV4518 => "
-//#define CONFIG_RMII
-#define CONFIG_AR8216_SWITCH 1
+
+//#define CONFIG_RMII 1
+#define CONFIG_RTL8306_SWITCH 1
#include "arcadyan-common.h"
--- /dev/null
+#ifndef __CONFIG_H_4520
+#define __CONFIG_H_4520
+
+#define CONFIG_ARV4520 1
+#define CONFIG_ARCADYAN "ARV4520PW"
+
+#define CONFIG_SYS_MAX_RAM 32*1024*1024
+#define CONFIG_USE_DDR_PSC_32 1
+#define CONFIG_SYS_PROMPT "ARV4520 => "
+#define CONFIG_RMII 1
+#define CONFIG_ADM6996_SWITCH 1
+#define CONFIG_EBU_GPIO 0x400
+
+#define CONFIG_BUTTON_PORT0
+#define CONFIG_BUTTON_PIN 11
+#define CONFIG_BUTTON_LEVEL 0
+
+#include "arcadyan-common.h"
+
+#endif
--- /dev/null
+#ifndef __CONFIG_H_4525
+#define __CONFIG_H_4525
+
+#define CONFIG_ARV4525 1
+#define CONFIG_ARCADYAN "ARV4525PW"
+
+#define CONFIG_SYS_MAX_RAM 32*1024*1024
+#define CONFIG_USE_DDR_PSC_32 1
+#define CONFIG_SYS_PROMPT "ARV4525 => "
+
+#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN 13
+#define CONFIG_BUTTON_LEVEL 0
+
+
+#include "arcadyan-common.h"
+
+#endif
#ifndef __CONFIG_H_452C
#define __CONFIG_H_452C
-#define CONFIG_ARV4518 1
+#define CONFIG_ARV452C 1
#define CONFIG_ARCADYAN "ARV452CPW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
+#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV452c => "
#define CONFIG_RMII 1
#define CONFIG_RTL8306_SWITCH 1
+#define CONFIG_EBU_GPIO 0xf00
+
+#define CONFIG_BUTTON_PORT0
+#define CONFIG_BUTTON_PIN 11
+#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#define CONFIG_ARCADYAN "ARV752DPW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
+#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW => "
-//#define CONFIG_RMII
-#define CONFIG_RTL8306_SWITCH 1
+#define CONFIG_RMII
+#define CONFIG_RTL8306G_SWITCH 1
//#define CONFIG_EBU_GPIO 0x2
#define CONFIG_SWITCH_PORT1
#define CONFIG_SWITCH_PIN 3
#define CONFIG_ARCADYAN "ARV752DPW22"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
+#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW22 => "
#define CONFIG_AR8216_SWITCH 1
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
+#undef CONFIG_PREBOOT
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
- "kernel_addr=0xb0050000\0" \
+ "kernel_addr=0xb0020000\0" \
"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-
-//#define CONFIG_CMD_ASKENV
-//#define CONFIG_CMD_DHCP
-//#define CONFIG_CMD_ELF
-#define CONFIG_CMD_PING
-//#define CONFIG_CMD_JFFS2
-//#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_PING
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_SYS_HUSH_PARSER
/*
* Miscellaneous configurable options
#define CONFIG_LZMA
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CONFIG_SYS_MEMTEST_END 0x80800000
#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#undef CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CONFIG_ENV_IS_IN_FLASH 1
/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0040000
+#define CONFIG_ENV_ADDR 0xB0010000
#define CONFIG_ENV_SIZE 0x10000
#ifdef CONFIG_FLASH_CFI_DRIVER
--- a/config.mk
+++ b/config.mk
-@@ -234,17 +234,42 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF
+@@ -234,17 +234,47 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF
#########################################################################
+
$(obj)%.s: %.S
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
++ #echo $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(obj)%.o: %.S
+ $(call MESSAGE, [AS], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
++ #echo $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.o: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
++ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.i: %.c
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
++ #echo $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.s: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
++ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
#########################################################################
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
-+ register struct arp_entry *tabptr;
++ register struct arp_entry *tabptr = 0;
+ /* Walk through the ARP mapping table and try to find an entry to
+ update. If none is found, the IP -> MAC address mapping is
+ inserted in the ARP table. */
+void
+uip_arp_out(void)
+{
-+ struct arp_entry *tabptr;
++ struct arp_entry *tabptr = 0;
+ /* Find the destination IP address in the ARP table and construct
+ the Ethernet header. If the destination IP addres isn't on the
+ local network, we use the default router's IP address instead.
SRCS := $(COBJS:.o=.c)
--- a/Makefile
+++ b/Makefile
-@@ -3414,6 +3414,37 @@
+@@ -3414,6 +3414,40 @@
## MIPS32 ifxcpe
#########################################################################
+ $(XECHO) "... with ramboot configuration" ; \
+ }
+ @if [ "$$(findstring flash,$$@)" ] ; then \
++ echo "#TEXT_BASE = 0xB0050000" >$(obj)board/arcadyan/config.tmp ; \
++ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_USE_DDR_RAM_CFG_psc166" >>$(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a $$(word 1,$$(subst _, ,$$@)) mips mips arcadyan "" danube
+endef
+
++$(eval $(call arcadyan, arv3527P%config))
+$(eval $(call arcadyan, arv4520PW%config))
+$(eval $(call arcadyan, arv452CPW%config))
+$(eval $(call arcadyan, arv4525PW%config))
--- /dev/null
+--- a/.gitignore
++++ b/.gitignore
+@@ -23,6 +23,11 @@
+ /u-boot.hex
+ /u-boot.map
+ /u-boot.bin
++/u-boot.bin.bz2
++/u-boot.bin.gz
++/u-boot.bin.lzma
++/u-boot.bin.lzo
++/u-boot.dis
+ /u-boot.srec
+ /u-boot.ldr
+ /u-boot.ldr.hex
+@@ -30,6 +35,20 @@
+ /u-boot.lds
+ /u-boot-onenand.bin
+ /u-boot-flexonenand.bin
++/u-boot-bootstrap
++/u-boot-bootstrap.hex
++/u-boot-bootstrap.map
++/u-boot-bootstrap.bin
++/u-boot-bootstrap.bin.bz2
++/u-boot-bootstrap.bin.gz
++/u-boot-bootstrap.bin.lzma
++/u-boot-bootstrap.bin.lzo
++/u-boot-bootstrap.dis
++/u-boot-bootstrap.srec
++/u-boot-bootstrap.ldr
++/u-boot-bootstrap.ldr.hex
++/u-boot-bootstrap.ldr.srec
++/u-boot-bootstrap.lds
+
+ #
+ # Generated files
+@@ -38,6 +57,7 @@
+ *.depend
+ /LOG
+ /errlog
++/.payload.s
+ /reloc_off
+
+ # stgit generated dirs
+@@ -63,3 +83,6 @@
+ /onenand_ipl/onenand-ipl*
+ /onenand_ipl/board/*/onenand*
+ /onenand_ipl/board/*/*.S
++examples/standalone/
++
++setvars
+--- a/Makefile
++++ b/Makefile
+@@ -183,6 +183,12 @@
+
+ OBJS := $(addprefix $(obj),$(OBJS))
+
++ifeq ($(CONFIG_BOOTSTRAP),y)
++BOOTSTRAP_OBJS = cpu/$(ARCH)/start_bootstrap.o
++
++BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_OBJS))
++endif
++
+ LIBS = lib_generic/libgeneric.a
+ LIBS += lib_generic/lzma/liblzma.a
+ LIBS += lib_generic/lzo/liblzo.a
+@@ -254,6 +260,25 @@
+ LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+ LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
+
++ifeq ($(CONFIG_BOOTSTRAP),y)
++BOOTSTRAP_LIBS = lib_generic/libgeneric_bootstrap.a
++BOOTSTRAP_LIBS += cpu/$(ARCH)/lib$(ARCH)_bootstrap.a
++BOOTSTRAP_LIBS += lib_$(ARCH)/lib$(ARCH)_bootstrap.a
++BOOTSTRAP_LIBS += common/libcommon_bootstrap.a
++BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_SERIAL) += drivers/serial/libserial.a
++
++BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_LZMA) += lib_generic/lzma/liblzma.a
++BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_LZO) += lib/lzo/liblzo.a
++BOOTSTRAP_LIBS += $(BOOTSTRAP_LIBS-y)
++
++BOOTSTRAP_LIBS := $(addprefix $(obj),$(BOOTSTRAP_LIBS))
++.PHONY : $(BOOTSTRAP_LIBS)
++
++BOOTSTRAP_LIBBOARD = board/$(BOARDDIR)/lib$(BOARD)_bootstrap.a
++BOOTSTRAP_LIBBOARD := $(addprefix $(obj),$(BOOTSTRAP_LIBBOARD))
++endif
++
++
+ # Add GCC lib
+ ifdef USE_PRIVATE_LIBGCC
+ ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+@@ -267,6 +292,9 @@
+ PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+ export PLATFORM_LIBS
+
++BOOTSTRAP_PLATFORM_LIBS += $(PLATFORM_LIBGCC)
++export BOOTSTRAP_PLATFORM_LIBS
++
+ # Special flags for CPP when processing the linker script.
+ # Pass the version down so we can handle backwards compatibility
+ # on the fly.
+@@ -289,12 +317,19 @@
+ __OBJS := $(subst $(obj),,$(OBJS))
+ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
+
++__BOOTSTRAP_OBJS := $(subst $(obj),,$(BOOTSTRAP_OBJS))
++__BOOTSTRAP_LIBS := $(subst $(obj),,$(BOOTSTRAP_LIBS)) $(subst $(obj),,$(BOOTSTRAP_LIBBOARD))
++
+ #########################################################################
+ #########################################################################
+
+ # Always append ALL so that arch config.mk's can add custom ones
+ ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
+
++ifeq ($(CONFIG_BOOTSTRAP),y)
++ALL += $(obj)u-boot-bootstrap.srec $(obj)u-boot-bootstrap.bin
++endif
++
+ all: $(ALL)
+
+ $(obj)u-boot.hex: $(obj)u-boot
+@@ -306,6 +341,19 @@
+ $(obj)u-boot.bin: $(obj)u-boot
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
++$(obj)u-boot.bin.gz: $(obj)u-boot.bin
++ gzip -c $< > $@
++
++$(obj)u-boot.bin.lzma: $(obj)u-boot.bin
++ echo lzma -e -z -c $< $@
++ lzma e $< $@
++
++$(obj)u-boot.bin.lzo: $(obj)u-boot.bin
++ lzop -9 -c $< > $@
++
++$(obj)u-boot.bin.bz2: $(obj)u-boot.bin
++ bzip2 --best -z -c $< > $@
++
+ $(obj)u-boot.ldr: $(obj)u-boot
+ $(CREATE_LDR_ENV)
+ $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
+@@ -335,12 +383,12 @@
+ $(obj)tools/ubsha1 $(obj)u-boot.bin
+
+ $(obj)u-boot.dis: $(obj)u-boot
+- $(OBJDUMP) -d $< > $@
++ $(OBJDUMP) -S -d $< > $@
+
+ GEN_UBOOT = \
+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+- cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
++ cd $(LNDIR) && $(LD) --gc-sections $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
+ -Map u-boot.map -o u-boot
+ $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+@@ -362,6 +410,120 @@
+ $(LIBBOARD): depend $(LIBS)
+ $(MAKE) -C $(dir $(subst $(obj),,$@))
+
++# Bootstrap targets
++
++ifeq ($(CONFIG_BOOTSTRAP),y)
++$(obj)u-boot-bootstrap.hex: $(obj)u-boot-bootstrap
++ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
++
++$(obj)u-boot-bootstrap.srec: $(obj)u-boot-bootstrap
++ $(OBJCOPY) -O srec $< $@
++
++$(obj)u-boot-bootstrap.bin: $(obj)u-boot-bootstrap
++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++ $(BOARD_SIZE_CHECK)
++
++$(obj)u-boot-bootstrap.bin.gz: $(obj)u-boot-bootstrap.bin
++ gzip -c $< > $@
++
++$(obj)u-boot-bootstrap.bin.lzma: $(obj)u-boot-bootstrap.bin
++ lzma -e -z -c $< > $@
++
++$(obj)u-boot.bin-bootstrap.lzo: $(obj)u-boot-bootstrap.bin
++ lzop -9 -c $< > $@
++
++$(obj)u-boot.bin-bootstrap.bz2: $(obj)u-boot-bootstrap.bin
++ bzip2 --best -z -c $< > $@
++
++$(obj)u-boot-bootstrap.ldr: $(obj)u-boot-bootstrap
++ $(CREATE_LDR_ENV)
++ $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
++ $(BOARD_SIZE_CHECK)
++
++$(obj)u-boot-bootstrap.ldr.hex: $(obj)u-boot-bootstrap.ldr
++ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
++
++$(obj)u-boot-bootstrap.ldr.srec: $(obj)u-boot-bootstrap.ldr
++ $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
++
++$(obj)u-boot-bootstrap.img: $(obj)u-boot-bootstrap.bin
++ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
++ -a $(CONFIG_BOOTSTRAP_BASE) -e 0 \
++ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
++ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
++ -d $< $@
++
++$(obj)u-boot-bootstrap.imx: $(obj)u-boot-bootstrap.bin
++ $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
++ -e $(CONFIG_BOOTSTRAP_BASE) -d $< $@
++
++$(obj)u-boot-bootstrap.kwb: $(obj)u-boot-bootstrap.bin
++ $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
++ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
++
++$(obj)u-boot-bootstrap.sha1: $(obj)u-boot-bootstrap.bin
++ $(obj)tools/ubsha1 $(obj)u-boot-bootstrap.bin
++
++$(obj)u-boot-bootstrap.dis: $(obj)u-boot-bootstrap
++ echo $(OBJDUMP) -S -d $< > $@
++ $(OBJDUMP) -S -d $< > $@
++
++PAYLOAD_FILE_BASE=$(obj)u-boot.bin
++ifeq ($(CONFIG_BOOTSTRAP_GZIP),y)
++PAYLOAD_FILE_EXT:=.gz
++endif
++ifeq ($(CONFIG_BOOTSTRAP_LZMA),y)
++PAYLOAD_FILE_EXT:=.lzma
++endif
++ifeq ($(CONFIG_BOOTSTRAP_LZO),y)
++PAYLOAD_FILE_EXT:=.lzo
++endif
++ifeq ($(CONFIG_BOOTSTRAP_BZIP2),y)
++PAYLOAD_FILE_EXT:=.bz2
++endif
++
++PAYLOAD_FILE := $(PAYLOAD_FILE_BASE)$(PAYLOAD_FILE_EXT)
++
++$(obj).payload.s: $(PAYLOAD_FILE)
++ echo ".globl payload_start" > $@
++ echo ".globl payload_end" >> $@
++ echo ".globl payload_size" >> $@
++ echo ".globl payload_uncsize" >> $@
++ echo .section .payload,\"a\",@progbits >> $@
++ echo "payload_size:" >> $@
++ echo -n ".word " >> $@
++ wc -c $(PAYLOAD_FILE) | cut -f1 -d' ' >> $@
++ echo "payload_uncsize:" >> $@
++ echo -n ".word " >> $@
++ wc -c $(obj)u-boot.bin | cut -f1 -d' ' >> $@
++ echo "payload_start:" >> $@
++ echo .incbin \"$(PAYLOAD_FILE)\" >> $@
++ echo "payload_end:" >> $@
++
++
++GEN_UBOOT_BOOTSTRAP = \
++ UNDEF_SYM=`$(OBJDUMP) -x $(BOOTSTRAP_LIBBOARD) $(BOOTSTRAP_LIBS) | \
++ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
++ cd $(LNDIR) && $(LD) --gc-sections $(BOOTSTRAP_LDFLAGS) $$UNDEF_SYM $(obj).payload.o $(__BOOTSTRAP_OBJS) \
++ --start-group $(__BOOTSTRAP_LIBS) --end-group $(BOOTSTRAP_PLATFORM_LIBS) \
++ -Map u-boot-bootstrap.map -o u-boot-bootstrap
++
++$(obj)u-boot-bootstrap: depend $(SUBDIRS) $(BOOTSTRAP_OBJS) $(BOOTSTRAP_LIBS) $(BOOTSTRAP_LDSCRIPT) $(obj)u-boot-bootstrap.lds $(obj).payload.o #$(BOOTSTRAP_LIBBOARD)
++ #echo "--------$(BOOTSTRAP_LIBBOARD)"
++ #echo "$(GEN_UBOOT_BOOTSTRAP)"
++ $(GEN_UBOOT_BOOTSTRAP)
++ifeq ($(CONFIG_KALLSYMS),y)
++ smap=`$(call SYSTEM_MAP,u-boot-bootstrap) | \
++ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
++ $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
++ -c common/system_map.c -o $(obj)common/system_map.o
++ $(GEN_UBOOT_BOOTSTRAP) $(obj)common/system_map.o
++endif
++
++$(BOOTSTRAP_LIBBOARD): depend $(BOOTSTRAP_LIBS)
++ $(MAKE) -C $(dir $(subst $(obj),,$@)) $(notdir $@)
++endif
++
+ $(SUBDIRS): depend
+ $(MAKE) -C $@ all
+
+@@ -371,6 +533,9 @@
+ $(obj)u-boot.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
++$(obj)u-boot-bootstrap.lds: $(BOOTSTRAP_LDSCRIPT)
++ $(CPP) $(CPPFLAGS) $(BOOTSTRAP_LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
++
+ $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+ $(MAKE) -C nand_spl/board/$(BOARDDIR) all
+
+@@ -3829,6 +3994,7 @@
+ $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
+ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
+ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
++ $(obj)u-boot-bootstrap.lds \
+ $(obj)lib_blackfin/u-boot.lds \
+ $(obj)u-boot.lds \
+ $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
+@@ -3853,6 +4019,12 @@
+ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
+ @rm -f $(obj)u-boot.kwb
+ @rm -f $(obj)u-boot.imx
++ @rm -f $(obj)u-boot.bin{.gz,.lzma,.lzo,.bz2}
++ @rm -f $(obj)u-boot-bootstrap $(obj)u-boot-bootstrap.map $(obj)u-boot-bootstrap.hex
++ @rm -f $(obj)u-boot-bootstrap.kwb
++ @rm -f $(obj)u-boot-bootstrap.imx
++ @rm -f $(obj)u-boot-bootstrap.bin{.gz,.lzma,.lzo,.bz2}
++ @rm -f $(obj).payload.s
+ @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
+ @rm -f $(obj)cpu/mpc824x/bedbug_603e.c
+ @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+--- a/lib_mips/config.mk
++++ b/lib_mips/config.mk
+@@ -47,6 +47,6 @@
+ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
+ # to RAM. $28 is always used as gp.
+ #
+-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
++PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -g
+ PLATFORM_CPPFLAGS += -msoft-float
+ PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
+--- /dev/null
++++ b/cpu/mips/reset.c
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <asm/mipsregs.h>
++#include <asm/reboot.h>
++
++void __attribute__((weak)) _machine_restart(void)
++{
++}
++
++int __attribute__((weak)) do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ _machine_restart();
++
++ fprintf(stderr, "*** reset failed ***\n");
++ return 0;
++}
+--- /dev/null
++++ b/cpu/mips/reset_bootstrap.c
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <asm/mipsregs.h>
++#include <asm/reboot.h>
++
++void __attribute__((weak)) _machine_restart(void)
++{
++}
++
++int __attribute__((weak)) do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ _machine_restart();
++
++ printf("*** reset failed ***\n");
++ return 0;
++}
+--- /dev/null
++++ b/cpu/mips/start_bootstrap.S
+@@ -0,0 +1,534 @@
++/*
++ * Startup Code for MIPS32 CPU-core base on start.S source
++ *
++ * Copyright (c) 2010 Industrie Dial Face S.p.A.
++ * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
++ *
++ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++//#include <generated/generic-asm-offsets.h>
++#include <config.h>
++#include <asm/regdef.h>
++//#include <asm/mipsregs.h>
++#define CP0_INDEX $0
++#define CP0_RANDOM $1
++#define CP0_ENTRYLO0 $2
++#define CP0_ENTRYLO1 $3
++#define CP0_CONF $3
++#define CP0_CONTEXT $4
++#define CP0_PAGEMASK $5
++#define CP0_WIRED $6
++#define CP0_INFO $7
++#define CP0_BADVADDR $8
++#define CP0_COUNT $9
++#define CP0_ENTRYHI $10
++#define CP0_COMPARE $11
++#define CP0_STATUS $12
++#define CP0_CAUSE $13
++#define CP0_EPC $14
++#define CP0_PRID $15
++#define CP0_EBASE $15,1
++#define CP0_CONFIG $16
++#define CP0_LLADDR $17
++#define CP0_WATCHLO $18
++#define CP0_WATCHHI $19
++#define CP0_XCONTEXT $20
++#define CP0_FRAMEMASK $21
++#define CP0_DIAGNOSTIC $22
++#define CP0_DEBUG $23
++#define CP0_DEPC $24
++#define CP0_PERFORMANCE $25
++#define CP0_ECC $26
++#define CP0_CACHEERR $27
++#define CP0_TAGLO $28
++#define CP0_TAGHI $29
++#define CP0_ERROREPC $30
++#define CP0_DESAVE $31
++#define ST0_CU0 0x10000000
++#define CONF_CM_UNCACHED 2
++#define CONF_CM_CACHABLE_NONCOHERENT 3
++#define EBASEB_CPUNUM 0
++#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM)
++#define MIPS_CONF7_RPS 4 //((unsigned long)(1) << 2)
++#define CONF_CM_CACHABLE_NONCOHERENT 3
++#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE
++#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT
++#endif
++
++ /*
++ * For the moment disable interrupts, mark the kernel mode and
++ * set ST0_KX so that the CPU does not spit fire when using
++ * 64-bit addresses.
++ */
++ .macro setup_c0_status set clr
++ .set push
++ mfc0 t0, CP0_STATUS
++ or t0, ST0_CU0 | \set | 0x1f | \clr
++ xor t0, 0x1f | \clr
++ mtc0 t0, CP0_STATUS
++ .set noreorder
++ sll zero, 3 # ehb
++ .set pop
++ .endm
++
++ .macro setup_c0_status_reset
++#ifdef CONFIG_64BIT
++ setup_c0_status ST0_KX 0
++#else
++ setup_c0_status 0 0
++#endif
++ .endm
++
++#define RVECENT(f,n) \
++ b f; nop
++#define XVECENT(f,bev) \
++ b f ; \
++ li k0,bev
++
++ .set noreorder
++
++ .globl _start
++ .text
++_start:
++ RVECENT(reset,0) /* U-boot entry point */
++ RVECENT(reset,1) /* software reboot */
++#if defined(CONFIG_INCA_IP)
++ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
++ .word 0x00000000 /* phase of the flash */
++#elif defined(CONFIG_PURPLE)
++ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
++ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
++#else
++ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
++ .word 0x00000000 /* phase of the flash */
++#endif
++ RVECENT(romReserved,3)
++ RVECENT(romReserved,4)
++ RVECENT(romReserved,5)
++ RVECENT(romReserved,6)
++ RVECENT(romReserved,7)
++ RVECENT(romReserved,8)
++ RVECENT(romReserved,9)
++ RVECENT(romReserved,10)
++ RVECENT(romReserved,11)
++ RVECENT(romReserved,12)
++ RVECENT(romReserved,13)
++ RVECENT(romReserved,14)
++ RVECENT(romReserved,15)
++ RVECENT(romReserved,16)
++ RVECENT(romReserved,17)
++ RVECENT(romReserved,18)
++ RVECENT(romReserved,19)
++ RVECENT(romReserved,20)
++ RVECENT(romReserved,21)
++ RVECENT(romReserved,22)
++ RVECENT(romReserved,23)
++ RVECENT(romReserved,24)
++ RVECENT(romReserved,25)
++ RVECENT(romReserved,26)
++ RVECENT(romReserved,27)
++ RVECENT(romReserved,28)
++ RVECENT(romReserved,29)
++ RVECENT(romReserved,30)
++ RVECENT(romReserved,31)
++ RVECENT(romReserved,32)
++ RVECENT(romReserved,33)
++ RVECENT(romReserved,34)
++ RVECENT(romReserved,35)
++ RVECENT(romReserved,36)
++ RVECENT(romReserved,37)
++ RVECENT(romReserved,38)
++ RVECENT(romReserved,39)
++ RVECENT(romReserved,40)
++ RVECENT(romReserved,41)
++ RVECENT(romReserved,42)
++ RVECENT(romReserved,43)
++ RVECENT(romReserved,44)
++ RVECENT(romReserved,45)
++ RVECENT(romReserved,46)
++ RVECENT(romReserved,47)
++ RVECENT(romReserved,48)
++ RVECENT(romReserved,49)
++ RVECENT(romReserved,50)
++ RVECENT(romReserved,51)
++ RVECENT(romReserved,52)
++ RVECENT(romReserved,53)
++ RVECENT(romReserved,54)
++ RVECENT(romReserved,55)
++ RVECENT(romReserved,56)
++ RVECENT(romReserved,57)
++ RVECENT(romReserved,58)
++ RVECENT(romReserved,59)
++ RVECENT(romReserved,60)
++ RVECENT(romReserved,61)
++ RVECENT(romReserved,62)
++ RVECENT(romReserved,63)
++ XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
++ RVECENT(romReserved,65)
++ RVECENT(romReserved,66)
++ RVECENT(romReserved,67)
++ RVECENT(romReserved,68)
++ RVECENT(romReserved,69)
++ RVECENT(romReserved,70)
++ RVECENT(romReserved,71)
++ RVECENT(romReserved,72)
++ RVECENT(romReserved,73)
++ RVECENT(romReserved,74)
++ RVECENT(romReserved,75)
++ RVECENT(romReserved,76)
++ RVECENT(romReserved,77)
++ RVECENT(romReserved,78)
++ RVECENT(romReserved,79)
++ XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
++ RVECENT(romReserved,81)
++ RVECENT(romReserved,82)
++ RVECENT(romReserved,83)
++ RVECENT(romReserved,84)
++ RVECENT(romReserved,85)
++ RVECENT(romReserved,86)
++ RVECENT(romReserved,87)
++ RVECENT(romReserved,88)
++ RVECENT(romReserved,89)
++ RVECENT(romReserved,90)
++ RVECENT(romReserved,91)
++ RVECENT(romReserved,92)
++ RVECENT(romReserved,93)
++ RVECENT(romReserved,94)
++ RVECENT(romReserved,95)
++ XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
++ RVECENT(romReserved,97)
++ RVECENT(romReserved,98)
++ RVECENT(romReserved,99)
++ RVECENT(romReserved,100)
++ RVECENT(romReserved,101)
++ RVECENT(romReserved,102)
++ RVECENT(romReserved,103)
++ RVECENT(romReserved,104)
++ RVECENT(romReserved,105)
++ RVECENT(romReserved,106)
++ RVECENT(romReserved,107)
++ RVECENT(romReserved,108)
++ RVECENT(romReserved,109)
++ RVECENT(romReserved,110)
++ RVECENT(romReserved,111)
++ XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
++ RVECENT(romReserved,113)
++ RVECENT(romReserved,114)
++ RVECENT(romReserved,115)
++ RVECENT(romReserved,116)
++ RVECENT(romReserved,116)
++ RVECENT(romReserved,118)
++ RVECENT(romReserved,119)
++ RVECENT(romReserved,120)
++ RVECENT(romReserved,121)
++ RVECENT(romReserved,122)
++ RVECENT(romReserved,123)
++ RVECENT(romReserved,124)
++ RVECENT(romReserved,125)
++ RVECENT(romReserved,126)
++ RVECENT(romReserved,127)
++
++ /* We hope there are no more reserved vectors!
++ * 128 * 8 == 1024 == 0x400
++ * so this is address R_VEC+0x400 == 0xbfc00400
++ */
++#if 1
++ XVECENT(romExcHandle,0x400); /* bfc00400: Int, CauseIV=1 */
++ RVECENT(romReserved,129);
++ RVECENT(romReserved,130);
++ RVECENT(romReserved,131);
++ RVECENT(romReserved,132);
++ RVECENT(romReserved,133);
++ RVECENT(romReserved,134);
++ RVECENT(romReserved,135);
++ RVECENT(romReserved,136);
++ RVECENT(romReserved,137);
++ RVECENT(romReserved,138);
++ RVECENT(romReserved,139);
++ RVECENT(romReserved,140);
++ RVECENT(romReserved,141);
++ RVECENT(romReserved,142);
++ RVECENT(romReserved,143);
++ XVECENT(romExcHandle,0x480); /* bfc00480: EJTAG debug exception */
++#elif defined(CONFIG_PURPLE)
++/* 0xbfc00400 */
++ .word 0xdc870000
++ .word 0xfca70000
++ .word 0x20840008
++ .word 0x20a50008
++ .word 0x20c6ffff
++ .word 0x14c0fffa
++ .word 0x00000000
++ .word 0x03e00008
++ .word 0x00000000
++ .word 0x00000000
++/* 0xbfc00428 */
++ .word 0xdc870000
++ .word 0xfca70000
++ .word 0x20840008
++ .word 0x20a50008
++ .word 0x20c6ffff
++ .word 0x14c0fffa
++ .word 0x00000000
++ .word 0x03e00008
++ .word 0x00000000
++ .word 0x00000000
++#endif /* CONFIG_PURPLE */
++ .align 4
++reset:
++#ifdef CONFIG_SYS_MIPS_MULTI_CPU
++ mfc0 k0, CP0_EBASE
++ and k0, EBASEF_CPUNUM
++ bne k0, zero, ifx_mips_handler_cpux
++ nop
++#endif
++ /* Clear watch registers.
++ */
++ mtc0 zero, CP0_WATCHLO
++ mtc0 zero, CP0_WATCHHI
++
++ /* WP(Watch Pending), SW0/1 should be cleared. */
++ mtc0 zero, CP0_CAUSE
++
++ setup_c0_status_reset
++#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC)
++ /* CONFIG7 register */
++ /* Erratum "RPS May Cause Incorrect Instruction Execution"
++ * for 24KEC and 34KC */
++ mfc0 k0, CP0_CONFIG, 7
++ li k1, MIPS_CONF7_RPS
++ or k0, k1
++ mtc0 k0, CP0_CONFIG, 7
++#endif
++
++ /* Init Timer */
++ mtc0 zero, CP0_COUNT
++ mtc0 zero, CP0_COMPARE
++
++ /* CONFIG0 register */
++ li t0, CONF_CM_UNCACHED
++ mtc0 t0, CP0_CONFIG
++
++ /* Initialize $gp.
++ */
++ bal 1f
++ nop
++ .word _gp
++1:
++ lw gp, 0(ra)
++
++ /* Initialize any external memory.
++ */
++ la t9, lowlevel_init
++ jalr t9
++ nop
++
++ /* Initialize caches...
++ */
++ la t9, mips_cache_reset
++ jalr t9
++ nop
++
++ /* ... and enable them.
++ */
++ li t0, CONF_CM_CACHABLE_NONCOHERENT /*CONFIG_SYS_MIPS_CACHE_OPER_MODE*/
++ mtc0 t0, CP0_CONFIG
++
++ /* Set up temporary stack.
++ */
++#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
++ li a0, CONFIG_SYS_INIT_SP_OFFSET
++ la t9, mips_cache_lock
++ jalr t9
++ nop
++#endif
++
++ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
++ la sp, 0(t0)
++
++ la t9, bootstrap_board_init_f
++ jr t9
++ nop
++
++/*
++ * void relocate_code (addr_sp, gd, addr_moni)
++ *
++ * This "function" does not return, instead it continues in RAM
++ * after relocating the monitor code.
++ *
++ * a0 = addr_sp
++ * a1 = gd
++ * a2 = destination address
++ */
++ .globl relocate_code
++ .ent relocate_code
++relocate_code:
++ move sp, a0 /* Set new stack pointer */
++
++ li t0, CONFIG_BOOTSTRAP_TEXT_BASE
++ la t3, in_ram
++ lw t2, -12(t3) /* t2 <-- uboot_end_data */
++ move t1, a2
++ move s2, a2 /* s2 <-- destination address */
++
++ /*
++ * Fix $gp:
++ *
++ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
++ */
++ move t6, gp
++ sub gp, CONFIG_BOOTSTRAP_TEXT_BASE
++ add gp, a2 /* gp now adjusted */
++ sub s1, gp, t6 /* s1 <-- relocation offset */
++
++ /*
++ * t0 = source address
++ * t1 = target address
++ * t2 = source end address
++ */
++
++ /*
++ * Save destination address and size for later usage in flush_cache()
++ */
++ move s0, a1 /* save gd in s0 */
++ move a0, t1 /* a0 <-- destination addr */
++ sub a1, t2, t0 /* a1 <-- size */
++
++ /* On the purple board we copy the code earlier in a special way
++ * in order to solve flash problems
++ */
++#ifndef CONFIG_PURPLE
++1:
++ lw t3, 0(t0)
++ sw t3, 0(t1)
++ addu t0, 4
++ ble t0, t2, 1b
++ addu t1, 4 /* delay slot */
++#endif
++
++ /* If caches were enabled, we would have to flush them here.
++ */
++
++ /* a0 & a1 are already set up for flush_cache(start, size) */
++ la t9, flush_cache
++ jalr t9
++ nop
++
++ /* Jump to where we've relocated ourselves.
++ */
++ addi t0, s2, in_ram - _start
++ jr t0
++ nop
++
++ .word _gp
++ .word _GLOBAL_OFFSET_TABLE_
++ .word uboot_end_data
++ .word uboot_end
++ .word num_got_entries
++
++in_ram:
++ /*
++ * Now we want to update GOT.
++ *
++ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
++ * generated by GNU ld. Skip these reserved entries from relocation.
++ */
++ lw t3, -4(t0) /* t3 <-- num_got_entries */
++ lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
++ lw t5, -20(t0) /* t5 <-- _gp */
++ sub t4, t5 /* compute offset*/
++ add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
++ addi t4, t4, 8 /* Skipping first two entries. */
++ li t2, 2
++1:
++ lw t1, 0(t4)
++ beqz t1, 2f
++ add t1, s1
++ sw t1, 0(t4)
++2:
++ addi t2, 1
++ blt t2, t3, 1b
++ addi t4, 4 /* delay slot */
++
++ /* Clear BSS.
++ */
++ lw t1, -12(t0) /* t1 <-- uboot_end_data */
++ lw t2, -8(t0) /* t2 <-- uboot_end */
++ add t1, s1 /* adjust pointers */
++ add t2, s1
++
++ sub t1, 4
++1:
++ addi t1, 4
++ bltl t1, t2, 1b
++ sw zero, 0(t1) /* delay slot */
++
++ move a0, s0 /* a0 <-- gd */
++ la t9, bootstrap_board_init_r
++ jr t9
++ move a1, s2 /* delay slot */
++
++ .end relocate_code
++
++/*
++ * void copy_and_jump (void)
++ *
++ * This function copies/unzips the u-boot image and runs it.
++ * This "function" does not return
++ *
++*/
++ .globl copy_and_jump
++ .ent copy_and_jump
++copy_and_jump:
++
++ /* copy_uboot(CONFIG_SYS_MONITOR_BASE, payload_uncsize, payload_start, payload_size) */
++ li a0, CONFIG_SYS_MONITOR_BASE
++ la a1, payload_uncsize
++ lw a1, 0(a1)
++ la a2, payload_start
++ la a3, payload_size
++ la t9, copy_uboot
++ jalr t9
++ lw a3, 0(a3) /* delay slot */
++
++ li t9, CONFIG_SYS_MONITOR_BASE
++ jr t9
++ nop
++
++ .end copy_and_jump
++
++ /* Exception handlers.
++ */
++romReserved:
++ b romReserved
++
++romExcHandle:
++ b romExcHandle
++#ifdef CONFIG_SYS_MIPS_MULTI_CPU
++/*
++ * Stop Slave CPUs
++ */
++ifx_mips_handler_cpux:
++ wait;
++ b ifx_mips_handler_cpux;
++ nop;
++#endif
+--- a/lib_mips/Makefile
++++ b/lib_mips/Makefile
+@@ -24,6 +24,9 @@
+ include $(TOPDIR)/config.mk
+
+ LIB = $(obj)lib$(ARCH).a
++BOOTSTRAP_LIB = $(obj)lib$(ARCH)_bootstrap.a
++
++BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
+
+ SOBJS-y +=
+
+@@ -35,12 +38,21 @@
+ endif
+ COBJS-y += time.o
+
+-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += board_bootstrap.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += time.o
++
++BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y) $(BOOTSTRAP_COBJS-y))
++
++SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
+ OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
++all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
+ $(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
++$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS)
++ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS)
++
+ #########################################################################
+
+ # defines $(obj).depend target
+--- /dev/null
++++ b/lib_mips/board_bootstrap.c
+@@ -0,0 +1,270 @@
++/*
++ * (C) Copyright 2010 Industrie Dial Face S.p.A.
++ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
++ *
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <malloc.h>
++#include <stdio_dev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++extern int timer_init(void);
++
++extern int incaip_set_cpuclk(void);
++
++extern ulong uboot_end_data;
++extern ulong uboot_end;
++
++#ifdef CONFIG_BOOTSTRAP_SERIAL
++static char *failed = "*** failed ***\n";
++#endif
++/*
++ * mips_io_port_base is the begin of the address space to which x86 style
++ * I/O ports are mapped.
++ */
++unsigned long mips_io_port_base = -1;
++
++int __board_early_init_f(void)
++{
++ /*
++ * Nothing to do in this dummy implementation
++ */
++ return 0;
++}
++
++int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f")));
++int bootstrap_board_early_init_f(void) __attribute__((weak, alias("board_early_init_f")));
++
++static int bootstrap_init_func_ram (void)
++{
++ if ((gd->ram_size = bootstrap_initdram (0)) > 0) {
++ return (0);
++ }
++#ifdef CONFIG_BOOTSTRAP_SERIAL
++ puts (failed);
++#endif
++ return (1);
++}
++
++static int bootstrap_display_banner(void)
++{
++#ifdef CONFIG_BOOTSTRAP_SERIAL
++ puts ("bootstrap...");
++#endif
++ return (0);
++}
++
++static int bootstrap_init_baudrate (void)
++{
++#if defined(CONFIG_BOOTSTRAP_BAUDRATE)
++ gd->baudrate = CONFIG_BOOTSTRAP_BAUDRATE;
++#else
++ gd->baudrate = CONFIG_BAUDRATE;
++#endif
++ return 0;
++}
++
++/*
++ * Breath some life into the board...
++ *
++ * The first part of initialization is running from Flash memory;
++ * its main purpose is to initialize the RAM so that we
++ * can relocate the monitor code to RAM.
++ */
++
++/*
++ * All attempts to come up with a "common" initialization sequence
++ * that works for all boards and architectures failed: some of the
++ * requirements are just _too_ different. To get rid of the resulting
++ * mess of board dependend #ifdef'ed code we now make the whole
++ * initialization sequence configurable to the user.
++ *
++ * The requirements for any new initalization function is simple: it
++ * receives a pointer to the "global data" structure as it's only
++ * argument, and returns an integer return code, where 0 means
++ * "continue" and != 0 means "fatal error, hang the system".
++ */
++typedef int (init_fnc_t) (void);
++
++static init_fnc_t *init_sequence[] = {
++ bootstrap_board_early_init_f,
++ timer_init,
++ bootstrap_init_baudrate,/* initialze baudrate settings */
++#ifdef CONFIG_BOOTSTRAP_SERIAL
++ serial_init, /* serial communications setup */
++#endif
++ bootstrap_display_banner, /* say that we are here */
++ bootstrap_checkboard,
++ bootstrap_init_func_ram,
++ NULL,
++};
++
++
++void bootstrap_board_init_f(ulong bootflag)
++{
++ gd_t gd_data, *id;
++ bd_t *bd;
++ init_fnc_t **init_fnc_ptr;
++ ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_BOOTSTRAP_TEXT_BASE;
++ ulong *s;
++
++ /* Pointer is writable since we allocated a register for it.
++ */
++ gd = &gd_data;
++ /* compiler optimization barrier needed for GCC >= 3.4 */
++ __asm__ __volatile__("": : :"memory");
++
++ memset ((void *)gd, 0, sizeof (gd_t));
++
++ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
++ if ((*init_fnc_ptr)() != 0) {
++ bootstrap_hang ();
++ }
++ }
++
++ /*
++ * Now that we have DRAM mapped and working, we can
++ * relocate the code and continue running from DRAM.
++ */
++ addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
++
++ /* We can reserve some RAM "on top" here.
++ */
++
++ /* round down to next 4 kB limit.
++ */
++ addr &= ~(4096 - 1);
++ debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
++
++ /* Reserve memory for U-Boot code, data & bss
++ * round down to next 16 kB limit
++ */
++ addr -= len;
++ addr &= ~(16 * 1024 - 1);
++
++ debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
++
++ /* Reserve memory for malloc() arena.
++ */
++ addr_sp = addr - CONFIG_SYS_MALLOC_LEN;
++ debug ("Reserving %dk for malloc() at: %08lx\n",
++ CONFIG_SYS_MALLOC_LEN >> 10, addr_sp);
++
++ /*
++ * (permanently) allocate a Board Info struct
++ * and a permanent copy of the "global" data
++ */
++ addr_sp -= sizeof(bd_t);
++ bd = (bd_t *)addr_sp;
++ gd->bd = bd;
++ debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
++ sizeof(bd_t), addr_sp);
++
++ addr_sp -= sizeof(gd_t);
++ id = (gd_t *)addr_sp;
++ debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
++ sizeof (gd_t), addr_sp);
++
++ /* Reserve memory for boot params.
++ */
++ addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN;
++ bd->bi_boot_params = addr_sp;
++ debug ("Reserving %dk for boot params() at: %08lx\n",
++ CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp);
++
++ /*
++ * Finally, we set up a new (bigger) stack.
++ *
++ * Leave some safety gap for SP, force alignment on 16 byte boundary
++ * Clear initial stack frame
++ */
++ addr_sp -= 16;
++ addr_sp &= ~0xF;
++ s = (ulong *)addr_sp;
++ *s-- = 0;
++ *s-- = 0;
++ addr_sp = (ulong)s;
++ debug ("Stack Pointer at: %08lx\n", addr_sp);
++
++ /*
++ * Save local variables to board info struct
++ */
++ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
++ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
++ bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
++
++ memcpy (id, (void *)gd, sizeof (gd_t));
++
++ /* On the purple board we copy the code in a special way
++ * in order to solve flash problems
++ */
++ relocate_code (addr_sp, id, addr);
++
++ /* NOTREACHED - relocate_code() does not return */
++}
++/************************************************************************
++ *
++ * This is the next part if the initialization sequence: we are now
++ * running from RAM and have a "normal" C environment, i. e. global
++ * data can be written, BSS has been cleared, the stack size in not
++ * that critical any more, etc.
++ *
++ ************************************************************************
++ */
++
++void bootstrap_board_init_r (gd_t *id, ulong dest_addr)
++{
++ extern void malloc_bin_reloc (void);
++ extern void copy_and_jump(void);
++
++ bd_t *bd;
++
++ gd = id;
++ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
++
++ debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
++
++ gd->reloc_off = dest_addr - CONFIG_BOOTSTRAP_TEXT_BASE;
++
++ bd = gd->bd;
++
++ /* The Malloc area is immediately below the monitor copy in DRAM */
++ mem_malloc_init(CONFIG_BOOTSTRAP_BASE + gd->reloc_off -
++ CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
++ malloc_bin_reloc();
++
++ copy_and_jump();
++
++ /* NOTREACHED - no way out of command loop except booting */
++}
++
++void bootstrap_hang (void)
++{
++#ifdef CONFIG_BOOTSTRAP_SERIAL
++ puts ("### ERROR ### Please RESET the board ###\n");
++#endif
++ for (;;);
++}
+--- a/common/Makefile
++++ b/common/Makefile
+@@ -24,6 +24,9 @@
+ include $(TOPDIR)/config.mk
+
+ LIB = $(obj)libcommon.a
++BOOTSTRAP_LIB = $(obj)libcommon_bootstrap.a
++
++BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
+
+ AOBJS =
+
+@@ -168,18 +171,27 @@
+ COBJS-$(CONFIG_UPDATE_TFTP) += update.o
+ COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += dlmalloc.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_SERIAL) += console_bootstrap.o
++
++BOOTSTRAP_COBJS := $(sort $(BOOTSTRAP_COBJS-y))
++BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS))
++
+
+ COBJS := $(sort $(COBJS-y))
+-SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
++SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
+
+ CPPFLAGS += -I..
+
+-all: $(LIB) $(AOBJS)
++all: $(LIB) $(BOOTSTRAP_LIB-y) $(AOBJS)
+
+ $(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
++$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS)
++ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS)
++
+ $(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc
+ $(CC) $(AFLAGS) -Wa,--no-warn \
+ -DENV_CRC=$(shell $(obj)../tools/envcrc) \
+--- /dev/null
++++ b/common/console_bootstrap.c
+@@ -0,0 +1,81 @@
++/*
++ * (C) Copyright 2000
++ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <stdarg.h>
++#include <malloc.h>
++
++/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
++
++int getc(void)
++{
++ /* Send directly to the handler */
++ return serial_getc();
++}
++
++int tstc(void)
++{
++ /* Send directly to the handler */
++ return serial_tstc();
++}
++
++void putc(const char c)
++{
++ /* Send directly to the handler */
++ serial_putc(c);
++}
++
++void puts(const char *s)
++{
++ serial_puts(s);
++}
++
++void printf(const char *fmt, ...)
++{
++ va_list args;
++ char printbuffer[CONFIG_SYS_PBSIZE];
++
++ va_start(args, fmt);
++
++ /* For this to work, printbuffer must be larger than
++ * anything we ever want to print.
++ */
++ vsprintf(printbuffer, fmt, args);
++ va_end(args);
++
++ /* Print the string */
++ puts(printbuffer);
++}
++
++void vprintf(const char *fmt, va_list args)
++{
++ char printbuffer[CONFIG_SYS_PBSIZE];
++
++ /* For this to work, printbuffer must be larger than
++ * anything we ever want to print.
++ */
++ vsprintf(printbuffer, fmt, args);
++
++ /* Print the string */
++ puts(printbuffer);
++}
+--- a/config.mk
++++ b/config.mk
+@@ -136,7 +136,7 @@
+ ARFLAGS = crv
+ endif
+ RELFLAGS= $(PLATFORM_RELFLAGS)
+-DBGFLAGS= -g # -DDEBUG
++DBGFLAGS= -g
+ OPTFLAGS= -Os #-fomit-frame-pointer
+ ifndef LDSCRIPT
+ #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+@@ -146,6 +146,11 @@
+ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+ endif
+ endif
++ifeq ($(CONFIG_BOOTSTRAP),y)
++ifndef BOOTSTRAP_LDSCRIPT
++BOOTSTRAP_LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-bootstrap.lds
++endif
++endif
+ OBJCFLAGS += --gap-fill=0xff
+
+ gccincdir := $(shell $(CC) -print-file-name=include)
+@@ -156,6 +161,10 @@
+ CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+ endif
+
++ifneq ($(CONFIG_BOOTSTRAP_TEXT_BASE),)
++CPPFLAGS += -DCONFIG_BOOTSTRAP_TEXT_BASE=$(CONFIG_BOOTSTRAP_TEXT_BASE)
++endif
++
+ ifneq ($(RESET_VECTOR_ADDRESS),)
+ CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS)
+ endif
+@@ -176,6 +185,7 @@
+ endif
+
+ CFLAGS += $(call cc-option,-fno-stack-protector)
++CFLAGS += $(call cc-option,-ffunction-sections)
+
+ # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
+ # this option have to be placed behind -Wall -- that's why it is here
+@@ -203,6 +213,13 @@
+ LDFLAGS += -Ttext $(TEXT_BASE)
+ endif
+
++ifeq ($(CONFIG_BOOTSTRAP),y)
++BOOTSTRAP_LDFLAGS += -Bstatic -T $(obj)u-boot-bootstrap.lds $(PLATFORM_LDFLAGS)
++ifneq ($(CONFIG_BOOTSTRAP_TEXT_BASE),)
++BOOTSTRAP_LDFLAGS += -Ttext $(CONFIG_BOOTSTRAP_TEXT_BASE)
++endif
++endif
++
+ # Location of a usable BFD library, where we define "usable" as
+ # "built for ${HOST}, supports ${TARGET}". Sensible values are
+ # - When cross-compiling: the root of the cross-environment
+--- a/include/common.h
++++ b/include/common.h
+@@ -722,6 +722,27 @@
+ int cpu_release(int nr, int argc, char *argv[]);
+ #endif
+
++/* Bootstrap specific code */
++#ifdef CONFIG_BOOTSTRAP
++void bootstrap_hang(void) __attribute__ ((noreturn));
++void bootstrap_board_init_f(ulong) __attribute__ ((noreturn));
++void bootstrap_board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
++int bootstrap_checkboard(void);
++
++int bootstrap_serial_init(void);
++void bootstrap_serial_exit(void);
++void bootstrap_serial_setbrg(void);
++void bootstrap_serial_putc(const char);
++void bootstrap_serial_putc_raw(const char);
++void bootstrap_serial_puts(const char *);
++int bootstrap_serial_getc(void);
++int bootstrap_serial_tstc(void);
++
++phys_size_t bootstrap_initdram (int);
++
++int copy_uboot(void *dst, size_t unc_size, void *src, size_t size);
++#endif
++
+ #endif /* __ASSEMBLY__ */
+
+ /* Put only stuff here that the assembler can digest */
+--- a/lib_generic/Makefile
++++ b/lib_generic/Makefile
+@@ -24,6 +24,9 @@
+ include $(TOPDIR)/config.mk
+
+ LIB = $(obj)libgeneric.a
++BOOTSTRAP_LIB = $(obj)libgeneric_bootstrap.a
++
++BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
+
+ COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
+ COBJS-$(CONFIG_BZIP2) += bzlib.o
+@@ -50,14 +53,37 @@
+ COBJS-y += vsprintf.o
+ COBJS-$(CONFIG_ZLIB) += zlib.o
+ COBJS-$(CONFIG_RBTREE) += rbtree.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += string.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += vsprintf.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += div64.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += ctype.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += time.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += bootstrap.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += zlib.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += gunzip.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += crc32.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_crctable.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_decompress.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_randtable.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_huffman.o
++
++BOOTSTRAP_COBJS := $(BOOTSTRAP_COBJS-y)
++BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS))
+
+ COBJS := $(COBJS-y)
+-SRCS := $(COBJS:.o=.c)
++SRCS := $(COBJS:.o=.c) $(BOOTSTRAP_COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(COBJS))
+
++all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB-y)
++
+ $(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
++$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS)
++ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS)
++
++
+ #########################################################################
+
+ # defines $(obj).depend target
+--- /dev/null
++++ b/lib_generic/bootstrap.c
+@@ -0,0 +1,95 @@
++/*
++ * (C) Copyright 2010 Industrie Dial Face S.p.A.
++ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
++ *
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <stdio_dev.h>
++
++#ifdef CONFIG_BOOTSTRAP_LZMA
++#include <lzma/LzmaTypes.h>
++#include <lzma/LzmaDec.h>
++#include <lzma/LzmaTools.h>
++#endif /* CONFIG_BOOTSTRAP_LZMA */
++
++#ifdef CONFIG_BOOTSTRAP_LZO
++#include <linux/lzo.h>
++#endif /* CONFIG_BOOTSTRAP_LZO */
++
++#ifdef CONFIG_BOOTSTRAP_BZIP2
++#include <bzlib.h>
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#if defined(CONFIG_BOOTSTRAP_SERIAL)
++static const char *algo =
++#if defined(CONFIG_BOOTSTRAP_GZIP)
++ "gzip";
++#elif defined(CONFIG_BOOTSTRAP_LZMA)
++ "lzma";
++#elif defined(CONFIG_BOOTSTRAP_LZO)
++ "lzo";
++#elif defined(CONFIG_BOOTSTRAP_BZIP2)
++ "bzip2";
++#else
++ "flat";
++#endif
++#endif
++
++int copy_uboot(void *dst, size_t unc_size, void *src, size_t size)
++{
++ int ret;
++ debug("copy from %p (%d) to %p (%d)\n", src, size, dst, unc_size);
++#if defined(CONFIG_BOOTSTRAP_SERIAL)
++ printf("Uncompressing payload (%s)...", algo);
++#endif
++#if defined(CONFIG_BOOTSTRAP_GZIP)
++ ret = gunzip(dst, unc_size, src, &size);
++#elif defined(CONFIG_BOOTSTRAP_LZMA)
++ SizeT outsize = unc_size;
++ ret = lzmaBuffToBuffDecompress(dst, &outsize, src, size);
++#elif defined(CONFIG_BOOTSTRAP_LZO)
++ uint unc_len = unc_size;
++ ret = lzop_decompress(src, size, dst, &unc_len);
++#elif defined(CONFIG_BOOTSTRAP_BZIP2)
++ uint unc_len = unc_size;
++ ret = BZ2_bzBuffToBuffDecompress ((char*)dst, &unc_len, (char *)src, size, CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
++#else
++ memcpy(dst, src, size);
++ ret = 0;
++#endif
++ if (ret) {
++#if defined(CONFIG_BOOTSTRAP_SERIAL)
++ printf("failed with error %d.\n", ret);
++#endif
++ bootstrap_hang();
++ } else {
++#if defined(CONFIG_BOOTSTRAP_SERIAL)
++ puts("done.\n");
++#endif
++ }
++ return ret;
++}
+--- a/lib_generic/lzma/Makefile
++++ b/lib_generic/lzma/Makefile
+@@ -32,7 +32,9 @@
+
+ CFLAGS += -D_LZMA_PROB32
+
+-COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o
++COBJS-$(CONFIG_LZMA)$(CONFIG_BOOTSTRAP_LZMA) += LzmaDec.o LzmaTools.o
++
++COBJS-y += $(COBJS-yy)
+
+ COBJS = $(COBJS-y)
+ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+--- a/lib_generic/lzo/Makefile
++++ b/lib_generic/lzo/Makefile
+@@ -27,7 +27,9 @@
+
+ SOBJS =
+
+-COBJS-$(CONFIG_LZO) += lzo1x_decompress.o
++COBJS-$(CONFIG_LZO)$(CONFIG_BOOTSTRAP_LZO) += lzo1x_decompress.o
++
++COBJS-y += $(OBJS-yy)
+
+ COBJS = $(COBJS-y)
+ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+--- a/cpu/mips/Makefile
++++ b/cpu/mips/Makefile
+@@ -24,25 +24,46 @@
+ include $(TOPDIR)/config.mk
+
+ LIB = $(obj)lib$(CPU).a
++BOOTSTRAP_LIB = $(obj)lib$(CPU)_bootstrap.a
++
++BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
+
+ START = start.o
+ SOBJS-y = cache.o
+-COBJS-y = cpu.o interrupts.o
++COBJS-y = cpu.o reset.o interrupts.o
+
+ SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o
+ COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o
++#COBJS-$(CONFIG_IFX_ASC) += ifx_asc.o
+ COBJS-$(CONFIG_PURPLE) += asc_serial.o
+ COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+
+-SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
++#BOOTSTRAP_START = start_bootstrap.o
++BOOTSTRAP_START-$(CONFIG_BOOTSTRAP) += start_bootstrap.o #$(BOOTSTRAP_START)
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += cpu.o interrupts.o reset_bootstrap.o
++BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) += cache.o
++BOOTSTRAP_COBJS-$(CONFIG_DANUBE) += danube-clock.o
++BOOTSTRAP_COBJS-$(CONFIG_AR9) += ar9-clock.o
++BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_SERIAL) += ifx_asc.o
++
++BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y) $(BOOTSTRAP_COBJS-y))
++BOOTSTRAP_START := $(addprefix $(obj),$(BOOTSTRAP_START-y))
++
++SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) $(BOOTSTRAP_START-y:.o=.S) $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
+ OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+ START := $(addprefix $(obj),$(START))
+
+-all: $(obj).depend $(START) $(LIB)
++all: $(obj).depend $(START) $(LIB) $(BOOTSTRAP_START-y) $(BOOTSTRAP_LIB-y)
+
+-$(LIB): $(OBJS)
++$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
++#$(BOOTSTRAP_START): $(obj).depend
++
++$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS)
++ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS)
++
++
+ #########################################################################
+
+ # defines $(obj).depend target
projects / openwrt / staging / chunkeey.git / commitdiff