mx35 timer: Switch to 32-kHz source

Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c
index 60000429c4c58681e39d12705a8c91cacb46a218..9680b7fde7bb18a6bb0615c698c76094a612b438 100644 (file)
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ b/arch/arm/cpu/arm1136/mx35/timer.c
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)        /* Software reset */
 #define GPTCR_FRR       (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (0x100<<6)        /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
+#define GPTCR_CLKSOURCE_32   (4<<6)    /* Clock source */
 #define GPTCR_TEN       (1)    /* Timer enable */
 
-#define        TIMER_FREQ_HZ   mxc_get_clock(MXC_IPG_CLK)
-
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, TIMER_FREQ_HZ);
+       do_div(tick, MXC_CLK32);
 
        return tick;
 }
 
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-       usec *= TIMER_FREQ_HZ;
-       do_div(usec, 1000000);
+       us = us * MXC_CLK32 + 999999;
+       do_div(us, 1000000);
 
-       return usec;
+       return us;
 }
 
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
 int timer_init(void)
 {
        int i;
        struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+       struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
 
        /* setup GP Timer 1 */
        writel(GPTCR_SWR, &gpt->ctrl);
-       for (i = 0; i < 100; i++)
-               writel(0, &gpt->ctrl);  /* We have no udelay by now */
 
-       writel(0, &gpt->pre);
-       /* Freerun Mode, PERCLK1 input */
-       writel(readl(&gpt->ctrl) |
-               GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-               &gpt->ctrl);
+       writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+       for (i = 0; i < 100; i++)
+               writel(0, &gpt->ctrl); /* We have no udelay by now */
+       writel(0, &gpt->pre); /* prescaler = 1 */
+       /* Freerun Mode, 32KHz input */
+       writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+                       &gpt->ctrl);
+       writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
 
        return 0;
 }
@@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-       return TIMER_FREQ_HZ;
+       return MXC_CLK32;
 }