--- /dev/null
+From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:29:51 +0800
+Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
+ data
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
+ include/linux/platform_data/spi-mt65xx.h | 17 --------------
+ 2 files changed, 11 insertions(+), 35 deletions(-)
+ delete mode 100644 include/linux/platform_data/spi-mt65xx.h
+
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -14,7 +14,6 @@
+ #include <linux/of.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/platform_device.h>
+-#include <linux/platform_data/spi-mt65xx.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi-mem.h>
+@@ -142,6 +141,8 @@ struct mtk_spi {
+ struct device *dev;
+ dma_addr_t tx_dma;
+ dma_addr_t rx_dma;
++ u32 sample_sel;
++ u32 get_tick_dly;
+ };
+
+ static const struct mtk_spi_compatible mtk_common_compat;
+@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m
+ .no_need_unprepare = true,
+ };
+
+-/*
+- * A piece of default chip info unless the platform
+- * supplies it.
+- */
+-static const struct mtk_chip_config mtk_default_chip_info = {
+- .sample_sel = 0,
+- .tick_delay = 0,
+-};
+-
+ static const struct of_device_id mtk_spi_of_match[] = {
+ { .compatible = "mediatek,spi-ipm",
+ .data = (void *)&mtk_ipm_compat,
+@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma
+ {
+ u16 cpha, cpol;
+ u32 reg_val;
+- struct mtk_chip_config *chip_config = spi->controller_data;
+ struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+ cpha = spi->mode & SPI_CPHA ? 1 : 0;
+@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma
+ else
+ reg_val &= ~SPI_CMD_CS_POL;
+
+- if (chip_config->sample_sel)
++ if (mdata->sample_sel)
+ reg_val |= SPI_CMD_SAMPLE_SEL;
+ else
+ reg_val &= ~SPI_CMD_SAMPLE_SEL;
+@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma
+ if (mdata->dev_comp->ipm_design) {
+ reg_val = readl(mdata->base + SPI_CMD_REG);
+ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
+- reg_val |= ((chip_config->tick_delay & 0x7)
++ reg_val |= ((mdata->get_tick_dly & 0x7)
+ << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
+ writel(reg_val, mdata->base + SPI_CMD_REG);
+ } else {
+ reg_val = readl(mdata->base + SPI_CFG1_REG);
+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
+- reg_val |= ((chip_config->tick_delay & 0x7)
++ reg_val |= ((mdata->get_tick_dly & 0x7)
+ << SPI_CFG1_GET_TICK_DLY_OFFSET);
+ writel(reg_val, mdata->base + SPI_CFG1_REG);
+ }
+ } else {
+ reg_val = readl(mdata->base + SPI_CFG1_REG);
+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
+- reg_val |= ((chip_config->tick_delay & 0x3)
++ reg_val |= ((mdata->get_tick_dly & 0x3)
+ << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
+ writel(reg_val, mdata->base + SPI_CFG1_REG);
+ }
+@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi
+ {
+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
+
+- if (!spi->controller_data)
+- spi->controller_data = (void *)&mtk_default_chip_info;
+-
+ if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
+ /* CS de-asserted, gpiolib will handle inversion */
+ gpiod_direction_output(spi->cs_gpiod, 0);
+@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform
+ mdata = spi_master_get_devdata(master);
+ mdata->dev_comp = of_id->data;
+
++ /* Set device configs to default first. Calibrate it later. */
++ mdata->sample_sel = 0;
++ mdata->get_tick_dly = 2;
++
+ if (mdata->dev_comp->enhance_timing)
+ master->mode_bits |= SPI_CS_HIGH;
+
+--- a/include/linux/platform_data/spi-mt65xx.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * MTK SPI bus driver definitions
+- *
+- * Copyright (c) 2015 MediaTek Inc.
+- * Author: Leilk Liu <leilk.liu@mediatek.com>
+- */
+-
+-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
+-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
+-
+-/* Board specific platform_data */
+-struct mtk_chip_config {
+- u32 sample_sel;
+- u32 tick_delay;
+-};
+-#endif
--- /dev/null
+From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:35:52 +0800
+Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++
+ include/linux/spi/spi.h | 42 ++++++++++++
+ 2 files changed, 179 insertions(+)
+
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -1234,6 +1234,70 @@ static int spi_transfer_wait(struct spi_
+ return 0;
+ }
+
++int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
++{
++ int datalen = ctlr->cal_rule->datalen;
++ int addrlen = ctlr->cal_rule->addrlen;
++ u8 *buf;
++ int ret;
++ int i;
++ struct list_head *cal_head, *listptr;
++ struct spi_cal_target *target;
++
++ /* Calculate calibration result */
++ int hit_val, total_hit, origin;
++ bool hit;
++
++ /* Make sure we can start calibration */
++ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
++ return 0;
++
++ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
++ if(!buf)
++ return -ENOMEM;
++
++ ret = ctlr->append_caldata(ctlr);
++ if (ret)
++ goto cal_end;
++
++ cal_head = ctlr->cal_target;
++ list_for_each(listptr, cal_head) {
++ target = list_entry(listptr, struct spi_cal_target, list);
++
++ hit = false;
++ hit_val = 0;
++ total_hit = 0;
++ origin = *target->cal_item;
++
++ for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
++ *target->cal_item = i;
++ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
++ if(ret)
++ break;
++ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
++ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
++ hit = true;
++ hit_val += i;
++ total_hit++;
++ dev_dbg(&spi->dev, "golden data matches data read!\n");
++ }
++ }
++ if(hit) {
++ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
++ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
++ } else {
++ *target->cal_item = origin;
++ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
++ }
++ }
++
++cal_end:
++ kfree(buf);
++ return ret? ret: 0;
++}
++EXPORT_SYMBOL_GPL(spi_do_calibration);
++
+ static void _spi_transfer_delay_ns(u32 ns)
+ {
+ if (!ns)
+@@ -2021,6 +2085,75 @@ void spi_flush_queue(struct spi_controll
+ /*-------------------------------------------------------------------------*/
+
+ #if defined(CONFIG_OF)
++static inline void alloc_cal_data(struct list_head **cal_target,
++ struct spi_cal_rule **cal_rule, bool enable)
++{
++ if(enable) {
++ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
++ INIT_LIST_HEAD(*cal_target);
++ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
++ } else {
++ kfree(*cal_target);
++ kfree(*cal_rule);
++ }
++}
++
++static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
++ struct device_node *nc)
++{
++ u32 value;
++ int rc;
++ const char *cal_mode;
++
++ rc = of_property_read_bool(nc, "spi-cal-enable");
++ if (rc)
++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
++ else
++ return 0;
++
++ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
++ if(!rc) {
++ if(strcmp("read-data", cal_mode) == 0){
++ ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
++ } else if(strcmp("read-pp", cal_mode) == 0) {
++ ctlr->cal_rule->mode = SPI_CAL_READ_PP;
++ return 0;
++ } else if(strcmp("read-sfdp", cal_mode) == 0){
++ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
++ return 0;
++ }
++ } else
++ goto err;
++
++ ctlr->cal_rule->datalen = 0;
++ rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
++ if(!rc && value > 0) {
++ ctlr->cal_rule->datalen = value;
++
++ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
++ rc = of_property_read_u8_array(nc, "spi-cal-data",
++ ctlr->cal_rule->match_data, value);
++ if(rc)
++ kfree(ctlr->cal_rule->match_data);
++ }
++
++ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
++ if(!rc && value > 0) {
++ ctlr->cal_rule->addrlen = value;
++
++ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
++ rc = of_property_read_u32_array(nc, "spi-cal-addr",
++ ctlr->cal_rule->addr, value);
++ if(rc)
++ kfree(ctlr->cal_rule->addr);
++ }
++ return 0;
++
++err:
++ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
++ return 0;
++}
++
+ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
+ struct device_node *nc)
+ {
+@@ -2139,6 +2272,10 @@ of_register_spi_device(struct spi_contro
+ if (rc)
+ goto err_out;
+
++ rc = of_spi_parse_cal_dt(ctlr, spi, nc);
++ if (rc)
++ goto err_out;
++
+ /* Store a pointer to the node in the device structure */
+ of_node_get(nc);
+ spi->dev.of_node = nc;
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -290,6 +290,40 @@ struct spi_driver {
+ struct device_driver driver;
+ };
+
++enum {
++ SPI_CAL_READ_DATA = 0,
++ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
++ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
++};
++
++struct nand_addr {
++ unsigned int lun;
++ unsigned int plane;
++ unsigned int eraseblock;
++ unsigned int page;
++ unsigned int dataoffs;
++};
++
++/**
++ * Read calibration rule from device dts node.
++ * Once calibration result matches the rule, we regard is as success.
++ */
++struct spi_cal_rule {
++ int datalen;
++ u8 *match_data;
++ int addrlen;
++ u32 *addr;
++ int mode;
++};
++
++struct spi_cal_target {
++ u32 *cal_item;
++ int cal_min; /* min of cal_item */
++ int cal_max; /* max of cal_item */
++ int step; /* Increase/decrease cal_item */
++ struct list_head list;
++};
++
+ static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
+ {
+ return drv ? container_of(drv, struct spi_driver, driver) : NULL;
+@@ -665,6 +699,11 @@ struct spi_controller {
+ void *dummy_rx;
+ void *dummy_tx;
+
++ /* For calibration */
++ int (*append_caldata)(struct spi_controller *ctlr);
++ struct list_head *cal_target;
++ struct spi_cal_rule *cal_rule;
++
+ int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
+
+ /*
+@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board
+ { return 0; }
+ #endif
+
++extern int spi_do_calibration(struct spi_controller *ctlr,
++ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
++
+ /* If you're hotplugging an adapter with devices (parport, usb, etc)
+ * use spi_new_device() to describe each device. You can also call
+ * spi_unregister_device() to start making that device vanish, but
--- /dev/null
+From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:37:55 +0800
+Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mem.c | 8 ++++++++
+ include/linux/spi/spi-mem.h | 4 ++++
+ 2 files changed, 12 insertions(+)
+
+--- a/drivers/spi/spi-mem.c
++++ b/drivers/spi/spi-mem.c
+@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
+ }
+ EXPORT_SYMBOL_GPL(spi_mem_exec_op);
+
++int spi_mem_do_calibration(struct spi_mem *mem,
++ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
++ void *priv)
++{
++ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
++}
++EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
++
+ /**
+ * spi_mem_get_name() - Return the SPI mem device name to be used by the
+ * upper layer if necessary
+--- a/include/linux/spi/spi-mem.h
++++ b/include/linux/spi/spi-mem.h
+@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
+ int spi_mem_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op);
+
++int spi_mem_do_calibration(struct spi_mem *mem,
++ int (*cal_read)(void *, u32 *, int, u8 *, int),
++ void *priv);
++
+ const char *spi_mem_get_name(struct spi_mem *mem);
+
+ struct spi_mem_dirmap_desc *
--- /dev/null
+From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:39:03 +0800
+Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
+ paramter
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int
+ return IRQ_HANDLED;
+ }
+
++static int mtk_spi_append_caldata(struct spi_controller *ctlr)
++{
++ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
++ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
++
++ cal_target->cal_item = &mdata->get_tick_dly;
++ cal_target->cal_min = 0;
++ cal_target->cal_max = 7;
++ cal_target->step = 1;
++
++ list_add(&cal_target->list, ctlr->cal_target);
++
++ return 0;
++}
++
+ static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+ {
+@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform
+ master->setup = mtk_spi_setup;
+ master->set_cs_timing = mtk_spi_set_hw_cs_timing;
+ master->use_gpio_descriptors = true;
++ master->append_caldata = mtk_spi_append_caldata;
+
+ of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
+ if (!of_id) {
--- /dev/null
+From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:39:56 +0800
+Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
+ spinand
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -967,6 +967,56 @@ static int spinand_manufacturer_match(st
+ return -ENOTSUPP;
+ }
+
++int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
++ struct spinand_device *spinand = (struct spinand_device *)priv;
++ struct device *dev = &spinand->spimem->spi->dev;
++ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
++ struct nand_pos pos;
++ struct nand_page_io_req req;
++ u8 status;
++ int ret;
++
++ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
++ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
++ return -EINVAL;
++ }
++
++ ret = spinand_reset_op(spinand);
++ if (ret)
++ return ret;
++
++ /* We should store our golden data in first target because
++ * we can't switch target at this moment.
++ */
++ pos = (struct nand_pos){
++ .target = 0,
++ .lun = *addr,
++ .plane = *(addr+1),
++ .eraseblock = *(addr+2),
++ .page = *(addr+3),
++ };
++
++ req = (struct nand_page_io_req){
++ .pos = pos,
++ .dataoffs = *(addr+4),
++ .datalen = readlen,
++ .databuf.in = buf,
++ .mode = MTD_OPS_AUTO_OOB,
++ };
++
++ ret = spinand_load_page_op(spinand, &req);
++ if (ret)
++ return ret;
++
++ ret = spinand_wait(spinand, &status);
++ if (ret < 0)
++ return ret;
++
++ ret = spi_mem_exec_op(spinand->spimem, &op);
++
++ return 0;
++}
++
+ static int spinand_id_detect(struct spinand_device *spinand)
+ {
+ u8 *id = spinand->id.data;
+@@ -1217,6 +1267,10 @@ static int spinand_init(struct spinand_d
+ if (!spinand->scratchbuf)
+ return -ENOMEM;
+
++ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
++ if (ret)
++ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
++
+ ret = spinand_detect(spinand);
+ if (ret)
+ goto err_free_bufs;
--- /dev/null
+From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
+From: "SkyLake.Huang" <skylake.huang@mediatek.com>
+Date: Thu, 23 Jun 2022 18:40:59 +0800
+Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
+ spi-nor
+
+Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
+---
+ drivers/mtd/nand/spi/core.c | 5 ++++-
+ drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -1008,7 +1008,10 @@ int spinand_cal_read(void *priv, u32 *ad
+ if (ret)
+ return ret;
+
+- ret = spinand_wait(spinand, &status);
++ ret = spinand_wait(spinand,
++ SPINAND_READ_INITIAL_DELAY_US,
++ SPINAND_READ_POLL_DELAY_US,
++ &status);
+ if (ret < 0)
+ return ret;
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -3060,6 +3060,18 @@ static void spi_nor_debugfs_init(struct
+ info->id_len, info->id);
+ }
+
++static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
++{
++ struct spi_nor *nor = (struct spi_nor *)priv;
++
++ nor->reg_proto = SNOR_PROTO_1_1_1;
++ nor->read_proto = SNOR_PROTO_1_1_1;
++ nor->read_opcode = SPINOR_OP_READ;
++ nor->read_dummy = 0;
++
++ return nor->controller_ops->read(nor, *addr, readlen, buf);
++}
++
+ static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
+ const char *name)
+ {
+@@ -3133,6 +3145,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+ if (!nor->bouncebuf)
+ return -ENOMEM;
+
++ if(nor->spimem)
++ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
++
+ info = spi_nor_get_flash_info(nor, name);
+ if (IS_ERR(info))
+ return PTR_ERR(info);
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
-@@ -1223,10 +1223,16 @@ static int mtk_spi_probe(struct platform
+@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform
goto err_disable_spi_hclk;
}
}
mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
-@@ -1277,6 +1283,8 @@ static int mtk_spi_probe(struct platform
+@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform
err_disable_runtime_pm:
pm_runtime_disable(&pdev->dev);
projects / openwrt / staging / dangole.git / commitdiff