rcar_gen3: plat: Fix cache line size

The CPU has cache line size of 64 Bytes, fix the cache line size.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
index 20fd712301df3d5df00763a402a3b464d81eee13..57399a248da42116f5f2e2857aa2b29e307e7d73 100644 (file)
--- a/plat/renesas/rcar/include/platform_def.h
+++ b/plat/renesas/rcar/include/platform_def.h
@@ -79,7 +79,7 @@
  *          Cortex-A53
  * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
  */
-#define PLATFORM_CACHE_LINE_SIZE       128
+#define PLATFORM_CACHE_LINE_SIZE       64
 #define PLATFORM_CLUSTER_COUNT         U(2)
 #define PLATFORM_CLUSTER0_CORE_COUNT   U(4)
 #define PLATFORM_CLUSTER1_CORE_COUNT   U(4)