Tegra210: Enable ECC reporting for B01 SKUs

This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.

Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c
Signed-off-by: Sam Payne <spayne@nvidia.com>

diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index b7f4b90ca13ee3eb9be999fc08e2c2d08958325e..ed30ff404e952d4318c91f7a8f0ea611b1a792c4 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -5,6 +5,7 @@
  */
 
 #include <assert.h>
+#include <cortex_a57.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
@@ -218,8 +219,17 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 
 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
+       const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
        uint32_t val;
 
+       /* platform parameter passed by the previous bootloader */
+       if (plat_params->l2_ecc_parity_prot_dis != 1) {
+               /* Enable ECC Parity Protection for Cortex-A57 CPUs */
+               val = read_l2ctlr_el1();
+               val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
+               write_l2ctlr_el1(val);
+       }
+
        /*
         * Check if we are exiting from SOC_POWERDN.
         */

diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index aefe1aa797493c017d8f3abb75548c4ff6ad042a..6246dde90f98e6dac708fecd6e36909aec9014c4 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -6,6 +6,7 @@
 
 #include <arch_helpers.h>
 #include <bpmp.h>
+#include <cortex_a57.h>
 #include <common/bl_common.h>
 #include <drivers/console.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
@@ -119,6 +120,17 @@ uint32_t plat_get_console_from_id(int id)
  ******************************************************************************/
 void plat_early_platform_setup(void)
 {
+       const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+       uint64_t val;
+
+       /* platform parameter passed by the previous bootloader */
+       if (plat_params->l2_ecc_parity_prot_dis != 1) {
+               /* Enable ECC Parity Protection for Cortex-A57 CPUs */
+               val = read_l2ctlr_el1();
+               val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
+               write_l2ctlr_el1(val);
+       }
+
        /* Initialize security engine driver */
        if (tegra_chipid_is_t210_b01()) {
                tegra_se_init();