by [plat/common/aarch64/platform_mp_stack.S] and
[plat/common/aarch64/platform_up_stack.S].
-* **#define : PCPU_DV_MEM_STACK_SIZE**
-
- Defines the coherent stack memory available to each CPU. This constant is used
- by [plat/common/aarch64/platform_mp_stack.S] and
- [plat/common/aarch64/platform_up_stack.S].
-
* **#define : FIRMWARE_WELCOME_STR**
Defines the character string printed by BL1 upon entry into the `bl1_main()`
cluster_id = 8-bit value in MPIDR at affinity level 1
-### Function : platform_set_coherent_stack()
-
- Argument : unsigned long
- Return : void
-
-A platform may need stack memory that is coherent with main memory to perform
-certain operations like:
-
-* Turning the MMU on, or
-* Flushing caches prior to powering down a CPU or cluster.
-
-Each BL stage allocates this coherent stack memory for each CPU in the
-`tzfw_coherent_mem` section.
-
-This function sets the current stack pointer to the coherent stack that
-has been allocated for the CPU specified by MPIDR. For BL images that only
-require a stack for the primary CPU the parameter is ignored. The size of
-the stack allocated to each CPU is specified by the platform defined constant
-`PCPU_DV_MEM_STACK_SIZE`.
-
-Common implementations of this function for the UP and MP BL images are
-provided in [plat/common/aarch64/platform_up_stack.S] and
-[plat/common/aarch64/platform_mp_stack.S]
-
-
### Function : platform_is_primary_cpu()
Argument : unsigned long
affinity level 0 (CPU), the platform port should power down affinity level 1
(the cluster) as well.
-This function is called with coherent stacks. This allows the PSCI
-implementation to flush caches at a given affinity level without running into
-stale stack state after turning off the caches. On ARMv8-A cache hits do not
-occur after the cache has been turned off.
-
#### plat_pm_ops.affinst_suspend()
Perform the platform specific setup to power off an affinity instance in the
resume execution by restoring this state when its powered on (see
`affinst_suspend_finish()`).
-This function is called with coherent stacks. This allows the PSCI
-implementation to flush caches at a given affinity level without running into
-stale stack state after turning off the caches. On ARMv8-A cache hits do not
-occur after the cache has been turned off.
-
#### plat_pm_ops.affinst_on_finish()
This function is called by the PSCI implementation after the calling CPU is
The `MPIDR` (first argument), `affinity level` (second argument) and `state`
(third argument) have a similar meaning as described in the previous operations.
-This function is called with coherent stacks. This allows the PSCI
-implementation to flush caches at a given affinity level without running into
-stale stack state after turning off the caches. On ARMv8-A cache hits do not
-occur after the cache has been turned off.
-
#### plat_pm_ops.affinst_on_suspend()
This function is called by the PSCI implementation after the calling CPU is
The `MPIDR` (first argument), `affinity level` (second argument) and `state`
(third argument) have a similar meaning as described in the previous operations.
-This function is called with coherent stacks. This allows the PSCI
-implementation to flush caches at a given affinity level without running into
-stale stack state after turning off the caches. On ARMv8-A cache hits do not
-occur after the cache has been turned off.
-
BL3-1 platform initialization code must also detect the system topology and
the state of each affinity instance in the topology. This information is
critical for the PSCI runtime service to function correctly. More details are
#include <platform_def.h>
- .local pcpu_dv_mem_stack
.local platform_normal_stacks
.weak platform_set_stack
.weak platform_get_stack
- .weak platform_set_coherent_stack
- /* -----------------------------------------------------
- * void platform_set_coherent_stack (unsigned long mpidr)
- *
- * For a given CPU, this function sets the stack pointer
- * to a stack allocated in device memory. This stack can
- * be used by C code which enables/disables the SCTLR.M
- * SCTLR.C bit e.g. while powering down a cpu
- * -----------------------------------------------------
- */
-func platform_set_coherent_stack
- mov x5, x30 // lr
- get_mp_stack pcpu_dv_mem_stack, PCPU_DV_MEM_STACK_SIZE
- mov sp, x0
- ret x5
-
/* -----------------------------------------------------
* unsigned long platform_get_stack (unsigned long mpidr)
*
ret x9
/* -----------------------------------------------------
- * Per-cpu stacks in normal memory.
- * Used for C code during runtime execution (when coherent
- * stacks are not required).
- * Each cpu gets a stack of PLATFORM_STACK_SIZE bytes.
+ * Per-cpu stacks in normal memory. Each cpu gets a
+ * stack of PLATFORM_STACK_SIZE bytes.
* -----------------------------------------------------
*/
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT
-
- /* -----------------------------------------------------
- * Per-cpu stacks in device memory.
- * Used for C code just before power down or right after
- * power up when the MMU or caches need to be turned on
- * or off.
- * Each cpu gets a stack of PCPU_DV_MEM_STACK_SIZE bytes.
- * -----------------------------------------------------
- */
-declare_stack pcpu_dv_mem_stack, tzfw_coherent_mem, \
- PCPU_DV_MEM_STACK_SIZE, PLATFORM_CORE_COUNT
#include <platform_def.h>
- .local pcpu_dv_mem_stack
.local platform_normal_stacks
.globl platform_set_stack
.globl platform_get_stack
- .globl platform_set_coherent_stack
-
-
- /* -----------------------------------------------------
- * void platform_set_coherent_stack (unsigned long)
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function sets the stack pointer to a stack
- * allocated in device memory.
- * -----------------------------------------------------
- */
-func platform_set_coherent_stack
- get_up_stack pcpu_dv_mem_stack, PCPU_DV_MEM_STACK_SIZE
- mov sp, x0
- ret
-
/* -----------------------------------------------------
* unsigned long platform_get_stack (unsigned long)
*/
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
PLATFORM_STACK_SIZE, 1
-
- /* -----------------------------------------------------
- * Single cpu stack in device/coherent memory.
- * PCPU_DV_MEM_STACK_SIZE bytes are allocated.
- * -----------------------------------------------------
- */
-declare_stack pcpu_dv_mem_stack, tzfw_coherent_mem, \
- PCPU_DV_MEM_STACK_SIZE, 1
* platform to decide whether the cluster is being turned off and take apt
* actions.
*
- * CAUTION: This function is called with coherent stacks so that caches can be
- * turned off, flushed and coherency disabled. There is no guarantee that caches
- * will remain turned on across calls to this function as each affinity level is
- * dealt with. So do not write & read global variables across calls. It will be
- * wise to do flush a write to the global to prevent unpredictable results.
+ * CAUTION: There is no guarantee that caches will remain turned on across calls
+ * to this function as each affinity level is dealt with. So do not write & read
+ * global variables across calls. It will be wise to do flush a write to the
+ * global to prevent unpredictable results.
******************************************************************************/
int fvp_affinst_off(unsigned long mpidr,
unsigned int afflvl,
* platform to decide whether the cluster is being turned off and take apt
* actions.
*
- * CAUTION: This function is called with coherent stacks so that caches can be
- * turned off, flushed and coherency disabled. There is no guarantee that caches
- * will remain turned on across calls to this function as each affinity level is
- * dealt with. So do not write & read global variables across calls. It will be
- * wise to do flush a write to the global to prevent unpredictable results.
+ * CAUTION: There is no guarantee that caches will remain turned on across calls
+ * to this function as each affinity level is dealt with. So do not write & read
+ * global variables across calls. It will be wise to do flush a write to the
+ * global to prevent unpredictable results.
******************************************************************************/
int fvp_affinst_suspend(unsigned long mpidr,
unsigned long sec_entrypoint,
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
-/* Size of coherent stacks for debug and release builds */
-#if DEBUG
-#define PCPU_DV_MEM_STACK_SIZE 0x400
-#else
-#define PCPU_DV_MEM_STACK_SIZE 0x300
-#endif
-
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
* the lowest to the highest affinity level implemented by the platform because
* to turn off affinity level X it is neccesary to turn off affinity level X - 1
* first.
- *
- * CAUTION: This function is called with coherent stacks so that coherency can
- * be turned off and caches can be flushed safely.
******************************************************************************/
int psci_afflvl_off(int start_afflvl,
int end_afflvl)
* the lowest to the highest affinity level implemented by the platform because
* to turn off affinity level X it is neccesary to turn off affinity level X - 1
* first.
- *
- * CAUTION: This function is called with coherent stacks so that coherency can
- * be turned off and caches can be flushed safely.
******************************************************************************/
int psci_afflvl_suspend(unsigned long entrypoint,
unsigned long context_id,
* the highest to the lowest affinity level implemented by the platform because
* to turn on affinity level X it is neccesary to turn on affinity level X + 1
* first.
- *
- * CAUTION: This function is called with coherent stacks so that coherency and
- * the mmu can be turned on safely.
******************************************************************************/
void psci_afflvl_power_on_finish(int start_afflvl,
int end_afflvl,
* upon whether it was resumed from suspend or simply
* turned on, call the common power on finisher with
* the handlers (chosen depending upon original state).
- * For ease, the finisher is called with coherent
- * stacks. This allows the cluster/cpu finishers to
- * enter coherency and enable the mmu without running
- * into issues. We switch back to normal stacks once
- * all this is done.
* -----------------------------------------------------
*/
func psci_aff_on_finish_entry
projects / project / bcm63xx / atf.git / commitdiff