drm/amdgpu/gfx10: use reset default for PA_SC_FIFO_SIZE

Recommended by the hw team.

Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2932ade7dbd055f46565218b2d614bd7b16a16ae..ccd5a4968a606ed62f3050af21faffc6ab284a11 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1544,24 +1544,6 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
 
        gfx_v10_0_init_compute_vmid(adev);
 
-       mutex_lock(&adev->grbm_idx_mutex);
-       /*
-        * making sure that the following register writes will be broadcasted
-        * to all the shaders
-        */
-       gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
-       tmp = REG_SET_FIELD(0, PA_SC_FIFO_SIZE, SC_FRONTEND_PRIM_FIFO_SIZE,
-                           adev->gfx.config.sc_prim_fifo_size_frontend);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_BACKEND_PRIM_FIFO_SIZE,
-                           adev->gfx.config.sc_prim_fifo_size_backend);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_HIZ_TILE_FIFO_SIZE,
-                           adev->gfx.config.sc_hiz_tile_fifo_size);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_EARLYZ_TILE_FIFO_SIZE,
-                           adev->gfx.config.sc_earlyz_tile_fifo_size);
-       WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, tmp);
-
-       mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,