num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
dwc->num_event_buffers = num;
- dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
- GFP_KERNEL);
+ dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ sizeof(*dwc->ev_buffs) * num);
if (!dwc->ev_buffs)
return -ENOMEM;
void dwc3_uboot_handle_interrupt(int index)
{
struct dwc3 *dwc = NULL;
+ int i;
+ struct dwc3_event_buffer *evt;
list_for_each_entry(dwc, &dwc3_list, list) {
if (dwc->index != index)
continue;
+ for (i = 0; i < dwc->num_event_buffers; i++) {
+ evt = dwc->ev_buffs[i];
+ dwc3_flush_cache((int)evt->buf, evt->length);
+ }
+
dwc3_gadget_uboot_handle_interrupt(dwc);
break;
}
| DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI);
+ dwc3_flush_cache((int)buf_dma, len);
+ dwc3_flush_cache((int)trb, sizeof(*trb));
+
memset(¶ms, 0, sizeof(params));
params.param0 = upper_32_bits(dwc->ep0_trb_addr);
params.param1 = lower_32_bits(dwc->ep0_trb_addr);
if (!r)
return;
+ dwc3_flush_cache((int)trb, sizeof(*trb));
+
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
dev_dbg(dwc->dev, "Setup Pending received");
transfer_size += (maxp - (transfer_size % maxp));
transferred = min_t(u32, ur->length,
transfer_size - length);
+ dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
memcpy(ur->buf, dwc->ep0_bounce, transferred);
} else {
transferred = ur->length - length;
list_del(&req->list);
req->trb = NULL;
+ dwc3_flush_cache((int)req->request.dma, req->request.length);
if (req->request.status == -EINPROGRESS)
req->request.status = status;
trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
trb->ctrl |= DWC3_TRB_CTRL_HWO;
+
+ dwc3_flush_cache((int)dma, length);
+ dwc3_flush_cache((int)trb, sizeof(*trb));
}
/*
slot %= DWC3_TRB_NUM;
trb = &dep->trb_pool[slot];
+ dwc3_flush_cache((int)trb, sizeof(*trb));
ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
event, status);
if (ret)
goto err1;
}
- dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
+ dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ DWC3_EP0_BOUNCE_SIZE);
if (!dwc->setup_buf) {
ret = -ENOMEM;
goto err2;
#include <asm/io.h>
+#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
static inline u32 dwc3_readl(void __iomem *base, u32 offset)
{
u32 offs = offset - DWC3_GLOBALS_REGS_START;
writel(value, base + offs);
}
+static inline void dwc3_flush_cache(int addr, int length)
+{
+ flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+}
#endif /* __DRIVERS_USB_DWC3_IO_H */