arm: omap-common: add secure smc entry

Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 528313584f3dd07e28dda860a2dc6d7404c7f074..66a3b3d26c950a48f29e19cab4681eff98f9e766 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -16,9 +16,10 @@
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
+.arch_extension sec
+
 #ifdef CONFIG_SPL
 ENTRY(save_boot_params)
-
        ldr     r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
        str     r0, [r1]
        b       save_boot_params_ret
@@ -26,14 +27,40 @@ ENDPROC(save_boot_params)
 #endif
 
 ENTRY(omap_smc1)
-       PUSH    {r4-r12, lr}    @ save registers - ROM code may pollute
+       push    {r4-r12, lr}    @ save registers - ROM code may pollute
                                @ our registers
-       MOV     r12, r0         @ Service
-       MOV     r0, r1          @ Argument
-       DSB
-       DMB
-       .word   0xe1600070      @ SMC #0 - hand assembled for GCC versions
-                               @ call ROM Code API for the service requested
+       mov     r12, r0         @ Service
+       mov     r0, r1          @ Argument
 
-       POP     {r4-r12, pc}
+       dsb
+       dmb
+       smc     0               @ SMC #0 to enter monitor mode
+                               @ call ROM Code API for the service requested
+       pop     {r4-r12, pc}
 ENDPROC(omap_smc1)
+
+ENTRY(omap_smc_sec)
+       push    {r4-r12, lr}    @ save registers - ROM code may pollute
+                               @ our registers
+       mov     r6, #0xFF       @ Indicate new Task call
+       mov     r12, #0x00      @ Secure Service ID in R12
+
+       dsb
+       dmb
+       smc     0               @ SMC #0 to enter monitor mode
+
+       b       omap_smc_sec_end @ exit at end of the service execution
+       nop
+
+       @ In case of IRQ happening in Secure, then ARM will branch here.
+       @ At that moment, IRQ will be pending and ARM will jump to Non Secure
+       @ IRQ handler
+       mov     r12, #0xFE
+
+       dsb
+       dmb
+       smc     0               @ SMC #0 to enter monitor mode
+
+omap_smc_sec_end:
+       pop     {r4-r12, pc}
+ENDPROC(omap_smc_sec)

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 07f384867eb03d43e75eefe8b001a7202033ad1c..605c549f0a5a647b84874d7cd4ed108762c63cc5 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -627,6 +627,12 @@ void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+/*
+ * Low-level helper function used when performing secure ROM calls on high-
+ * security (HS) device variants by doing a specially-formed smc entry.
+ */
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+
 void enable_edma3_clocks(void);
 void disable_edma3_clocks(void);