drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_pipeline_powergating()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b0805b1e7b299eab40ce86365f467e61a4124b82..1a928f6dc8011a26a5eaebd8f4b0350a1f060d39 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1896,10 +1896,9 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
        uint32_t data, default_data;
 
        default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-       if (enable == true)
-               data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-       else
-               data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
+       data = REG_SET_FIELD(data, RLC_PG_CNTL,
+                            GFX_PIPELINE_PG_ENABLE,
+                            enable ? 1 : 0);
        if(default_data != data)
                WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);