drm/amd/display: Program front end first when set mode.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a5c72dbc2dccb3f2f6fdebecc2a5bd70b11596f9..f9bac11d39500917f726e7108040da657ff9f546 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -763,16 +763,6 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
        if (!dcb->funcs->is_accelerated_mode(dcb))
                dc->hwss.enable_accelerated_mode(dc);
 
-       dc->hwss.ready_shared_resources(dc, context);
-
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               pipe = &context->res_ctx.pipe_ctx[i];
-               dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
-       }
-       result = dc->hwss.apply_ctx_to_hw(dc, context);
-
-       program_timing_sync(dc, context);
-
        for (i = 0; i < context->stream_count; i++) {
                const struct dc_sink *sink = context->streams[i]->sink;
 
@@ -798,6 +788,13 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
                        }
                }
 
+               for (j = 0; j < MAX_PIPES; j++) {
+                       pipe = &context->res_ctx.pipe_ctx[j];
+
+                       if (!pipe->top_pipe && pipe->stream == context->streams[i])
+                               dc->hwss.pipe_control_lock(dc, pipe, false);
+               }
+
                CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
                                context->streams[i]->timing.h_addressable,
                                context->streams[i]->timing.v_addressable,
@@ -806,6 +803,16 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
                                context->streams[i]->timing.pix_clk_khz);
        }
 
+       dc->hwss.ready_shared_resources(dc, context);
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               pipe = &context->res_ctx.pipe_ctx[i];
+               dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
+       }
+       result = dc->hwss.apply_ctx_to_hw(dc, context);
+
+       program_timing_sync(dc, context);
+
        dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
        dc_release_state(dc->current_state);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 86cfab33feea84474170f0b0bf7e8c820575e1c1..84d9d202d3b5bdb1ba830e8d015aae0b5c6ae191 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2283,8 +2283,6 @@ static void update_dchubp_dpp(
         */
        REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
 
-       dc->hwss.update_plane_addr(dc, pipe_ctx);
-
        mi->funcs->mem_input_setup(
                mi,
                &pipe_ctx->dlg_regs,
@@ -2353,6 +2351,8 @@ static void update_dchubp_dpp(
                &plane_state->dcc,
                plane_state->horizontal_mirror);
 
+       dc->hwss.update_plane_addr(dc, pipe_ctx);
+
        if (is_pipe_tree_visible(pipe_ctx))
                mi->funcs->set_blank(mi, false);
 }
@@ -2556,6 +2556,7 @@ static void dcn10_apply_ctx_for_surface(
                        old_pipe_ctx->top_pipe = NULL;
                        old_pipe_ctx->bottom_pipe = NULL;
                        old_pipe_ctx->plane_state = NULL;
+                       old_pipe_ctx->stream = NULL;
 
                        dm_logger_write(dc->ctx->logger, LOG_DC,
                                        "Reset mpcc for pipe %d\n",