Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 73ed38230c3e6da91a6c867ca406afbb6c434f69..6a334411988e9e91fb50614dfbfe5303ccd07cd2 100644 (file)
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -145,6 +145,11 @@ For Cortex-A75, the following errata build flags are defined :
 -  ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
     CPU. This needs to be enabled only for revision r0p0 of the CPU.
 
+For Cortex-A76, the following errata build flags are defined :
+
+-  ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
 DSU Errata Workarounds
 ----------------------
 

diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 27db74e418d8f19741a961dab4afda02b4f69759..8438fa6cf9a3951a72931765fa7469702892ead9 100644 (file)
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -189,6 +189,34 @@ vector_entry cortex_a76_serror_aarch32
        b       serror_aarch32
 end_vector_entry cortex_a76_serror_aarch32
 
+       /* --------------------------------------------------
+        * Errata Workaround for Cortex A76 Errata #1130799.
+        * This applies only to revision <= r2p0 of Cortex A76.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * --------------------------------------------------
+        */
+func errata_a76_1130799_wa
+       /*
+        * Compare x0 against revision r2p0
+        */
+       mov     x17, x30
+       bl      check_errata_1130799
+       cbz     x0, 1f
+       mrs     x1, CORTEX_A76_CPUACTLR2_EL1
+       orr     x1, x1 ,#(1 << 59)
+       msr     CORTEX_A76_CPUACTLR2_EL1, x1
+       isb
+1:
+       ret     x17
+endfunc errata_a76_1130799_wa
+
+func check_errata_1130799
+       mov     x1, #0x20
+       b       cpu_rev_var_ls
+endfunc check_errata_1130799
+
 func check_errata_cve_2018_3639
 #if WORKAROUND_CVE_2018_3639
        mov     x0, #ERRATA_APPLIES
@@ -206,8 +234,18 @@ func cortex_a76_disable_wa_cve_2018_3639
        ret
 endfunc cortex_a76_disable_wa_cve_2018_3639
 
+       /* -------------------------------------------------
+        * The CPU Ops reset function for Cortex-A76.
+        * Shall clobber: x0-x19
+        * -------------------------------------------------
+        */
 func cortex_a76_reset_func
        mov     x19, x30
+       bl      cpu_get_rev_var
+
+#if ERRATA_A76_1130799
+       bl      errata_a76_1130799_wa
+#endif
 
 #if WORKAROUND_CVE_2018_3639
        /* If the PE implements SSBS, we don't need the dynamic workaround */
@@ -271,6 +309,7 @@ func cortex_a76_errata_report
         * Report all errata. The revision-variant information is passed to
         * checking functions of each errata.
         */
+       report_errata ERRATA_A76_1130799, cortex_a76, 1130799
        report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
        report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
 

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index a7acd2f8b01c4b527212918c6bbf5dc66d81c61a..4fe8ea1ba5496d7a5e3796ba134df32b574151e7 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -131,6 +131,10 @@ ERRATA_A75_764081  ?=0
 # only to revision <= r0p0 of the Cortex A75 cpu.
 ERRATA_A75_790748      ?=0
 
+# Flag to apply erratum 1130799 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Cortex A76 cpu.
+ERRATA_A76_1130799     ?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202      ?=1
@@ -212,6 +216,10 @@ $(eval $(call add_define,ERRATA_A75_764081))
 $(eval $(call assert_boolean,ERRATA_A75_790748))
 $(eval $(call add_define,ERRATA_A75_790748))
 
+# Process ERRATA_A76_1130799 flag
+$(eval $(call assert_boolean,ERRATA_A76_1130799))
+$(eval $(call add_define,ERRATA_A76_1130799))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))