drm/i915/gen10+: use the SKL code for reading WM latencies
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 9 Aug 2017 20:52:43 +0000 (13:52 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 10 Aug 2017 20:59:27 +0000 (13:59 -0700)
Gen 10 should use the exact same code as Gen 9, so change the check to
take this into consideration, and also assume that future platforms
will run this code.

Also add a MISSING_CASE(), just in case we do something wrong, instead
of silently failing.

Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-1-rodrigo.vivi@intel.com
drivers/gpu/drm/i915/intel_pm.c

index 4a75b673b85f492bce2748bd6b929282deb82dbd..04697faee4e6f05f1f7807286b40eaa80e163c58 100644 (file)
@@ -2778,7 +2778,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
                                  uint16_t wm[8])
 {
-       if (IS_GEN9(dev_priv)) {
+       if (INTEL_GEN(dev_priv) >= 9) {
                uint32_t val;
                int ret, i;
                int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2838,7 +2838,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
                }
 
                /*
-                * WaWmMemoryReadLatency:skl,glk
+                * WaWmMemoryReadLatency:skl+,glk
                 *
                 * punit doesn't take into account the read latency so we need
                 * to add 2us to the various latency levels we retrieve from the
@@ -2877,6 +2877,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
                wm[0] = 7;
                wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
                wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
+       } else {
+               MISSING_CASE(INTEL_DEVID(dev_priv));
        }
 }