hwif->resetproc = tmp_hwif->resetproc;
hwif->maskproc = tmp_hwif->maskproc;
hwif->quirkproc = tmp_hwif->quirkproc;
- hwif->busproc = tmp_hwif->busproc;
hwif->ata_input_data = tmp_hwif->ata_input_data;
hwif->ata_output_data = tmp_hwif->ata_output_data;
case HDIO_SET_BUSSTATE:
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
- if (HWIF(drive)->busproc)
- return HWIF(drive)->busproc(drive, (int)arg);
return -EOPNOTSUPP;
default:
return -EINVAL;
hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
}
-/*
- * Set/get power state for a drive.
- * NOTE: affects both drives on each channel.
- *
- * When we turn the power back on, we need to re-initialize things.
- */
-#define TRISTATE_BIT 0x8000
-
-static int hpt3xx_busproc(ide_drive_t *drive, int state)
-{
- ide_hwif_t *hwif = HWIF(drive);
- struct pci_dev *dev = to_pci_dev(hwif->dev);
- u8 mcr_addr = hwif->select_data + 2;
- u8 resetmask = hwif->channel ? 0x80 : 0x40;
- u8 bsr2 = 0;
- u16 mcr = 0;
-
- hwif->bus_state = state;
-
- /* Grab the status. */
- pci_read_config_word(dev, mcr_addr, &mcr);
- pci_read_config_byte(dev, 0x59, &bsr2);
-
- /*
- * Set the state. We don't set it if we don't need to do so.
- * Make sure that the drive knows that it has failed if it's off.
- */
- switch (state) {
- case BUSSTATE_ON:
- if (!(bsr2 & resetmask))
- return 0;
- hwif->drives[0].failures = hwif->drives[1].failures = 0;
-
- pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
- pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
- return 0;
- case BUSSTATE_OFF:
- if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
- return 0;
- mcr &= ~TRISTATE_BIT;
- break;
- case BUSSTATE_TRISTATE:
- if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
- return 0;
- mcr |= TRISTATE_BIT;
- break;
- default:
- return -EINVAL;
- }
-
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
-
- pci_write_config_word(dev, mcr_addr, mcr);
- pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
- return 0;
-}
-
/**
* hpt37x_calibrate_dpll - calibrate the DPLL
* @dev: PCI device
hwif->quirkproc = &hpt3xx_quirkproc;
hwif->maskproc = &hpt3xx_maskproc;
- hwif->busproc = &hpt3xx_busproc;
hwif->udma_filter = &hpt3xx_udma_filter;
hwif->mdma_filter = &hpt3xx_mdma_filter;
clear interrupts */
hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
hwif->quirkproc = NULL;
- hwif->busproc = NULL;
hwif->INB = &sgiioc4_INB;
return 0;
}
-/**
- * sil_sata_busproc - bus isolation IOCTL
- * @drive: drive to isolate/restore
- * @state: bus state to set
- *
- * Used by the SII3112 to handle bus isolation. As this is a
- * SATA controller the work required is quite limited, we
- * just have to clean up the statistics
- */
-
-static int sil_sata_busproc(ide_drive_t * drive, int state)
-{
- ide_hwif_t *hwif = HWIF(drive);
- struct pci_dev *dev = to_pci_dev(hwif->dev);
- u32 stat_config = 0;
- unsigned long addr = siimage_selreg(hwif, 0);
-
- if (hwif->mmio)
- stat_config = readl((void __iomem *)addr);
- else
- pci_read_config_dword(dev, addr, &stat_config);
-
- switch (state) {
- case BUSSTATE_ON:
- hwif->drives[0].failures = 0;
- hwif->drives[1].failures = 0;
- break;
- case BUSSTATE_OFF:
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
- break;
- case BUSSTATE_TRISTATE:
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
- break;
- default:
- return -EINVAL;
- }
- hwif->bus_state = state;
- return 0;
-}
-
/**
* sil_sata_reset_poll - wait for SATA reset
* @drive: drive we are resetting
if (sata) {
static int first = 1;
- hwif->busproc = &sil_sata_busproc;
hwif->reset_poll = &sil_sata_reset_poll;
hwif->pre_reset = &sil_sata_pre_reset;
hwif->udma_filter = &sil_sata_udma_filter;
ide_dma_start(drive);
}
-static int tc86c001_busproc(ide_drive_t *drive, int state)
-{
- ide_hwif_t *hwif = HWIF(drive);
- unsigned long sc_base = hwif->config_data;
- u16 scr1;
-
- /* System Control 1 Register bit 11 (ATA Hard Reset) read */
- scr1 = inw(sc_base + 0x00);
-
- switch (state) {
- case BUSSTATE_ON:
- if (!(scr1 & 0x0800))
- return 0;
- scr1 &= ~0x0800;
-
- hwif->drives[0].failures = hwif->drives[1].failures = 0;
- break;
- case BUSSTATE_OFF:
- if (scr1 & 0x0800)
- return 0;
- scr1 |= 0x0800;
-
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
- break;
- default:
- return -EINVAL;
- }
-
- /* System Control 1 Register bit 11 (ATA Hard Reset) write */
- outw(scr1, sc_base + 0x00);
- return 0;
-}
-
static u8 __devinit tc86c001_cable_detect(ide_hwif_t *hwif)
{
struct pci_dev *dev = to_pci_dev(hwif->dev);
hwif->set_pio_mode = &tc86c001_set_pio_mode;
hwif->set_dma_mode = &tc86c001_set_mode;
- hwif->busproc = &tc86c001_busproc;
-
hwif->cable_detect = tc86c001_cable_detect;
if (!hwif->dma_base)
void (*maskproc)(ide_drive_t *, int);
/* check host's drive quirk list */
void (*quirkproc)(ide_drive_t *);
- /* driver soft-power interface */
- int (*busproc)(ide_drive_t *, int);
#endif
u8 (*mdma_filter)(ide_drive_t *);
u8 (*udma_filter)(ide_drive_t *);